Add gops agent

vendor/golang.org/x/arch/ppc64/ppc64asm/LICENSE

@@ -0,0 +1,27 @@
+Copyright (c) 2015 The Go Authors. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+
+   * Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above
+copyright notice, this list of conditions and the following disclaimer
+in the documentation and/or other materials provided with the
+distribution.
+   * Neither the name of Google Inc. nor the names of its
+contributors may be used to endorse or promote products derived from
+this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

vendor/golang.org/x/arch/ppc64/ppc64asm/decode.go

@@ -0,0 +1,179 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"encoding/binary"
+	"fmt"
+	"log"
+)
+
+const debugDecode = false
+
+// instFormat is a decoding rule for one specific instruction form.
+// a uint32 instruction ins matches the rule if ins&Mask == Value
+// DontCare bits should be zero, but the machine might not reject
+// ones in those bits, they are mainly reserved for future expansion
+// of the instruction set.
+// The Args are stored in the same order as the instruction manual.
+type instFormat struct {
+	Op       Op
+	Mask     uint32
+	Value    uint32
+	DontCare uint32
+	Args     [5]*argField
+}
+
+// argField indicate how to decode an argument to an instruction.
+// First parse the value from the BitFields, shift it left by Shift
+// bits to get the actual numerical value.
+type argField struct {
+	Type  ArgType
+	Shift uint8
+	BitFields
+}
+
+// Parse parses the Arg out from the given binary instruction i.
+func (a argField) Parse(i uint32) Arg {
+	switch a.Type {
+	default:
+		return nil
+	case TypeUnknown:
+		return nil
+	case TypeReg:
+		return R0 + Reg(a.BitFields.Parse(i))
+	case TypeCondRegBit:
+		return Cond0LT + CondReg(a.BitFields.Parse(i))
+	case TypeCondRegField:
+		return CR0 + CondReg(a.BitFields.Parse(i))
+	case TypeFPReg:
+		return F0 + Reg(a.BitFields.Parse(i))
+	case TypeVecReg:
+		return V0 + Reg(a.BitFields.Parse(i))
+	case TypeVecSReg:
+		return VS0 + Reg(a.BitFields.Parse(i))
+	case TypeSpReg:
+		return SpReg(a.BitFields.Parse(i))
+	case TypeImmSigned:
+		return Imm(a.BitFields.ParseSigned(i) << a.Shift)
+	case TypeImmUnsigned:
+		return Imm(a.BitFields.Parse(i) << a.Shift)
+	case TypePCRel:
+		return PCRel(a.BitFields.ParseSigned(i) << a.Shift)
+	case TypeLabel:
+		return Label(a.BitFields.ParseSigned(i) << a.Shift)
+	case TypeOffset:
+		return Offset(a.BitFields.ParseSigned(i) << a.Shift)
+	}
+}
+
+type ArgType int8
+
+const (
+	TypeUnknown      ArgType = iota
+	TypePCRel                // PC-relative address
+	TypeLabel                // absolute address
+	TypeReg                  // integer register
+	TypeCondRegBit           // conditional register bit (0-31)
+	TypeCondRegField         // conditional register field (0-7)
+	TypeFPReg                // floating point register
+	TypeVecReg               // vector register
+	TypeVecSReg              // VSX register
+	TypeSpReg                // special register (depends on Op)
+	TypeImmSigned            // signed immediate
+	TypeImmUnsigned          // unsigned immediate/flag/mask, this is the catch-all type
+	TypeOffset               // signed offset in load/store
+	TypeLast                 // must be the last one
+)
+
+func (t ArgType) String() string {
+	switch t {
+	default:
+		return fmt.Sprintf("ArgType(%d)", int(t))
+	case TypeUnknown:
+		return "Unknown"
+	case TypeReg:
+		return "Reg"
+	case TypeCondRegBit:
+		return "CondRegBit"
+	case TypeCondRegField:
+		return "CondRegField"
+	case TypeFPReg:
+		return "FPReg"
+	case TypeVecReg:
+		return "VecReg"
+	case TypeVecSReg:
+		return "VecSReg"
+	case TypeSpReg:
+		return "SpReg"
+	case TypeImmSigned:
+		return "ImmSigned"
+	case TypeImmUnsigned:
+		return "ImmUnsigned"
+	case TypePCRel:
+		return "PCRel"
+	case TypeLabel:
+		return "Label"
+	case TypeOffset:
+		return "Offset"
+	}
+}
+
+func (t ArgType) GoString() string {
+	s := t.String()
+	if t > 0 && t < TypeLast {
+		return "Type" + s
+	}
+	return s
+}
+
+var (
+	// Errors
+	errShort   = fmt.Errorf("truncated instruction")
+	errUnknown = fmt.Errorf("unknown instruction")
+)
+
+var decoderCover []bool
+
+// Decode decodes the leading bytes in src as a single instruction using
+// byte order ord.
+func Decode(src []byte, ord binary.ByteOrder) (inst Inst, err error) {
+	if len(src) < 4 {
+		return inst, errShort
+	}
+	if decoderCover == nil {
+		decoderCover = make([]bool, len(instFormats))
+	}
+	inst.Len = 4 // only 4-byte instructions are supported
+	ui := ord.Uint32(src[:inst.Len])
+	inst.Enc = ui
+	for i, iform := range instFormats {
+		if ui&iform.Mask != iform.Value {
+			continue
+		}
+		if ui&iform.DontCare != 0 {
+			if debugDecode {
+				log.Printf("Decode(%#x): unused bit is 1 for Op %s", ui, iform.Op)
+			}
+			// to match GNU objdump (libopcodes), we ignore don't care bits
+		}
+		for i, argfield := range iform.Args {
+			if argfield == nil {
+				break
+			}
+			inst.Args[i] = argfield.Parse(ui)
+		}
+		inst.Op = iform.Op
+		if debugDecode {
+			log.Printf("%#x: search entry %d", ui, i)
+			continue
+		}
+		break
+	}
+	if inst.Op == 0 {
+		return inst, errUnknown
+	}
+	return inst, nil
+}

vendor/golang.org/x/arch/ppc64/ppc64asm/doc.go

@@ -0,0 +1,6 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+// Package ppc64asm implements decoding of 64-bit PowerPC machine code.
+package ppc64asm

vendor/golang.org/x/arch/ppc64/ppc64asm/field.go

@@ -0,0 +1,84 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"fmt"
+	"strings"
+)
+
+// A BitField is a bit-field in a 32-bit word.
+// Bits are counted from 0 from the MSB to 31 as the LSB.
+type BitField struct {
+	Offs uint8 // the offset of the left-most bit.
+	Bits uint8 // length in bits.
+}
+
+func (b BitField) String() string {
+	if b.Bits > 1 {
+		return fmt.Sprintf("[%d:%d]", b.Offs, int(b.Offs+b.Bits)-1)
+	} else if b.Bits == 1 {
+		return fmt.Sprintf("[%d]", b.Offs)
+	} else {
+		return fmt.Sprintf("[%d, len=0]", b.Offs)
+	}
+}
+
+// Parse extracts the bitfield b from i, and return it as an unsigned integer.
+// Parse will panic if b is invalid.
+func (b BitField) Parse(i uint32) uint32 {
+	if b.Bits > 32 || b.Bits == 0 || b.Offs > 31 || b.Offs+b.Bits > 32 {
+		panic(fmt.Sprintf("invalid bitfiled %v", b))
+	}
+	return (i >> (32 - b.Offs - b.Bits)) & ((1 << b.Bits) - 1)
+}
+
+// ParseSigned extracts the bitfield b from i, and return it as a signed integer.
+// ParseSigned will panic if b is invalid.
+func (b BitField) ParseSigned(i uint32) int32 {
+	u := int32(b.Parse(i))
+	return u << (32 - b.Bits) >> (32 - b.Bits)
+}
+
+// BitFields is a series of BitFields representing a single number.
+type BitFields []BitField
+
+func (bs BitFields) String() string {
+	ss := make([]string, len(bs))
+	for i, bf := range bs {
+		ss[i] = bf.String()
+	}
+	return fmt.Sprintf("<%s>", strings.Join(ss, "|"))
+}
+
+func (bs *BitFields) Append(b BitField) {
+	*bs = append(*bs, b)
+}
+
+// parse extracts the bitfields from i, concatenate them and return the result
+// as an unsigned integer and the total length of all the bitfields.
+// parse will panic if any bitfield in b is invalid, but it doesn't check if
+// the sequence of bitfields is reasonable.
+func (bs BitFields) parse(i uint32) (u uint32, Bits uint8) {
+	for _, b := range bs {
+		u = (u << b.Bits) | b.Parse(i)
+		Bits += b.Bits
+	}
+	return u, Bits
+}
+
+// Parse extracts the bitfields from i, concatenate them and return the result
+// as an unsigned integer. Parse will panic if any bitfield in b is invalid.
+func (bs BitFields) Parse(i uint32) uint32 {
+	u, _ := bs.parse(i)
+	return u
+}
+
+// Parse extracts the bitfields from i, concatenate them and return the result
+// as a signed integer. Parse will panic if any bitfield in b is invalid.
+func (bs BitFields) ParseSigned(i uint32) int32 {
+	u, l := bs.parse(i)
+	return int32(u) << (32 - l) >> (32 - l)
+}

vendor/golang.org/x/arch/ppc64/ppc64asm/gnu.go

@@ -0,0 +1,125 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"bytes"
+	"fmt"
+	"strings"
+)
+
+// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils.
+// This form typically matches the syntax defined in the Power ISA Reference Manual.
+func GNUSyntax(inst Inst) string {
+	var buf bytes.Buffer
+	if inst.Op == 0 {
+		return "error: unkown instruction"
+	}
+	buf.WriteString(inst.Op.String())
+	sep := " "
+	for i, arg := range inst.Args[:] {
+		if arg == nil {
+			break
+		}
+		text := gnuArg(&inst, i, arg)
+		if text == "" {
+			continue
+		}
+		buf.WriteString(sep)
+		sep = ","
+		buf.WriteString(text)
+	}
+	return buf.String()
+}
+
+// gnuArg formats arg (which is the argIndex's arg in inst) according to GNU rules.
+// NOTE: because GNUSyntax is the only caller of this func, and it receives a copy
+//       of inst, it's ok to modify inst.Args here.
+func gnuArg(inst *Inst, argIndex int, arg Arg) string {
+	// special cases for load/store instructions
+	if _, ok := arg.(Offset); ok {
+		if argIndex+1 == len(inst.Args) || inst.Args[argIndex+1] == nil {
+			panic(fmt.Errorf("wrong table: offset not followed by register"))
+		}
+	}
+	switch arg := arg.(type) {
+	case Reg:
+		if isLoadStoreOp(inst.Op) && argIndex == 1 && arg == R0 {
+			return "0"
+		}
+		return arg.String()
+	case CondReg:
+		if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") {
+			return "" // don't show cr0 for cmp instructions
+		} else if arg >= CR0 {
+			return fmt.Sprintf("cr%d", int(arg-CR0))
+		}
+		bit := [4]string{"lt", "gt", "eq", "so"}[(arg-Cond0LT)%4]
+		if arg <= Cond0SO {
+			return bit
+		}
+		return fmt.Sprintf("4*cr%d+%s", int(arg-Cond0LT)/4, bit)
+	case Imm:
+		return fmt.Sprintf("%d", arg)
+	case SpReg:
+		return fmt.Sprintf("%d", int(arg))
+	case PCRel:
+		return fmt.Sprintf(".%+#x", int(arg))
+	case Label:
+		return fmt.Sprintf("%#x", uint32(arg))
+	case Offset:
+		reg := inst.Args[argIndex+1].(Reg)
+		removeArg(inst, argIndex+1)
+		if reg == R0 {
+			return fmt.Sprintf("%d(0)", int(arg))
+		}
+		return fmt.Sprintf("%d(r%d)", int(arg), reg-R0)
+	}
+	return fmt.Sprintf("???(%v)", arg)
+}
+
+// removeArg removes the arg in inst.Args[index].
+func removeArg(inst *Inst, index int) {
+	for i := index; i < len(inst.Args); i++ {
+		if i+1 < len(inst.Args) {
+			inst.Args[i] = inst.Args[i+1]
+		} else {
+			inst.Args[i] = nil
+		}
+	}
+}
+
+// isLoadStoreOp returns true if op is a load or store instruction
+func isLoadStoreOp(op Op) bool {
+	switch op {
+	case LBZ, LBZU, LBZX, LBZUX:
+		return true
+	case LHZ, LHZU, LHZX, LHZUX:
+		return true
+	case LHA, LHAU, LHAX, LHAUX:
+		return true
+	case LWZ, LWZU, LWZX, LWZUX:
+		return true
+	case LWA, LWAX, LWAUX:
+		return true
+	case LD, LDU, LDX, LDUX:
+		return true
+	case LQ:
+		return true
+	case STB, STBU, STBX, STBUX:
+		return true
+	case STH, STHU, STHX, STHUX:
+		return true
+	case STW, STWU, STWX, STWUX:
+		return true
+	case STD, STDU, STDX, STDUX:
+		return true
+	case STQ:
+		return true
+	case LHBRX, LWBRX, STHBRX, STWBRX:
+		return true
+	}
+	return false
+}

vendor/golang.org/x/arch/ppc64/ppc64asm/inst.go

@@ -0,0 +1,344 @@
+// Copyright 2014 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"bytes"
+	"fmt"
+)
+
+type Inst struct {
+	Op   Op     // Opcode mnemonic
+	Enc  uint32 // Raw encoding bits
+	Len  int    // Length of encoding in bytes.
+	Args Args   // Instruction arguments, in Power ISA manual order.
+}
+
+func (i Inst) String() string {
+	var buf bytes.Buffer
+	buf.WriteString(i.Op.String())
+	for j, arg := range i.Args {
+		if arg == nil {
+			break
+		}
+		if j == 0 {
+			buf.WriteString(" ")
+		} else {
+			buf.WriteString(", ")
+		}
+		buf.WriteString(arg.String())
+	}
+	return buf.String()
+}
+
+// An Op is an instruction operation.
+type Op uint16
+
+func (o Op) String() string {
+	if int(o) >= len(opstr) || opstr[o] == "" {
+		return fmt.Sprintf("Op(%d)", int(o))
+	}
+	return opstr[o]
+}
+
+// An Arg is a single instruction argument, one of these types: Reg, CondReg, SpReg, Imm, PCRel, Label, or Offset.
+type Arg interface {
+	IsArg()
+	String() string
+}
+
+// An Args holds the instruction arguments.
+// If an instruction has fewer than 4 arguments,
+// the final elements in the array are nil.
+type Args [5]Arg
+
+// A Reg is a single register. The zero value means R0, not the absence of a register.
+// It also includes special registers.
+type Reg uint16
+
+const (
+	_ Reg = iota
+	R0
+	R1
+	R2
+	R3
+	R4
+	R5
+	R6
+	R7
+	R8
+	R9
+	R10
+	R11
+	R12
+	R13
+	R14
+	R15
+	R16
+	R17
+	R18
+	R19
+	R20
+	R21
+	R22
+	R23
+	R24
+	R25
+	R26
+	R27
+	R28
+	R29
+	R30
+	R31
+	F0
+	F1
+	F2
+	F3
+	F4
+	F5
+	F6
+	F7
+	F8
+	F9
+	F10
+	F11
+	F12
+	F13
+	F14
+	F15
+	F16
+	F17
+	F18
+	F19
+	F20
+	F21
+	F22
+	F23
+	F24
+	F25
+	F26
+	F27
+	F28
+	F29
+	F30
+	F31
+	V0 // VSX extension, F0 is V0[0:63].
+	V1
+	V2
+	V3
+	V4
+	V5
+	V6
+	V7
+	V8
+	V9
+	V10
+	V11
+	V12
+	V13
+	V14
+	V15
+	V16
+	V17
+	V18
+	V19
+	V20
+	V21
+	V22
+	V23
+	V24
+	V25
+	V26
+	V27
+	V28
+	V29
+	V30
+	V31
+	VS0
+	VS1
+	VS2
+	VS3
+	VS4
+	VS5
+	VS6
+	VS7
+	VS8
+	VS9
+	VS10
+	VS11
+	VS12
+	VS13
+	VS14
+	VS15
+	VS16
+	VS17
+	VS18
+	VS19
+	VS20
+	VS21
+	VS22
+	VS23
+	VS24
+	VS25
+	VS26
+	VS27
+	VS28
+	VS29
+	VS30
+	VS31
+	VS32
+	VS33
+	VS34
+	VS35
+	VS36
+	VS37
+	VS38
+	VS39
+	VS40
+	VS41
+	VS42
+	VS43
+	VS44
+	VS45
+	VS46
+	VS47
+	VS48
+	VS49
+	VS50
+	VS51
+	VS52
+	VS53
+	VS54
+	VS55
+	VS56
+	VS57
+	VS58
+	VS59
+	VS60
+	VS61
+	VS62
+	VS63
+)
+
+func (Reg) IsArg() {}
+func (r Reg) String() string {
+	switch {
+	case R0 <= r && r <= R31:
+		return fmt.Sprintf("r%d", int(r-R0))
+	case F0 <= r && r <= F31:
+		return fmt.Sprintf("f%d", int(r-F0))
+	case V0 <= r && r <= V31:
+		return fmt.Sprintf("v%d", int(r-V0))
+	case VS0 <= r && r <= VS63:
+		return fmt.Sprintf("vs%d", int(r-VS0))
+	default:
+		return fmt.Sprintf("Reg(%d)", int(r))
+	}
+}
+
+// CondReg is a bit or field in the conditon register.
+type CondReg int8
+
+const (
+	_ CondReg = iota
+	// Condition Regster bits
+	Cond0LT
+	Cond0GT
+	Cond0EQ
+	Cond0SO
+	Cond1LT
+	Cond1GT
+	Cond1EQ
+	Cond1SO
+	Cond2LT
+	Cond2GT
+	Cond2EQ
+	Cond2SO
+	Cond3LT
+	Cond3GT
+	Cond3EQ
+	Cond3SO
+	Cond4LT
+	Cond4GT
+	Cond4EQ
+	Cond4SO
+	Cond5LT
+	Cond5GT
+	Cond5EQ
+	Cond5SO
+	Cond6LT
+	Cond6GT
+	Cond6EQ
+	Cond6SO
+	Cond7LT
+	Cond7GT
+	Cond7EQ
+	Cond7SO
+	// Condition Register Fields
+	CR0
+	CR1
+	CR2
+	CR3
+	CR4
+	CR5
+	CR6
+	CR7
+)
+
+func (CondReg) IsArg() {}
+func (c CondReg) String() string {
+	switch {
+	default:
+		return fmt.Sprintf("CondReg(%d)", int(c))
+	case c >= CR0:
+		return fmt.Sprintf("CR%d", int(c-CR0))
+	case c >= Cond0LT && c < CR0:
+		return fmt.Sprintf("Cond%d%s", int((c-Cond0LT)/4), [4]string{"LT", "GT", "EQ", "SO"}[(c-Cond0LT)%4])
+	}
+}
+
+// SpReg is a special register, its meaning depends on Op.
+type SpReg uint16
+
+const (
+	SpRegZero SpReg = 0
+)
+
+func (SpReg) IsArg() {}
+func (s SpReg) String() string {
+	return fmt.Sprintf("SpReg(%d)", int(s))
+}
+
+// PCRel is a PC-relative offset, used only in branch instructions.
+type PCRel int32
+
+func (PCRel) IsArg() {}
+func (r PCRel) String() string {
+	return fmt.Sprintf("PC%+#x", int32(r))
+}
+
+// A Label is a code (text) address, used only in absolute branch instructions.
+type Label uint32
+
+func (Label) IsArg() {}
+func (l Label) String() string {
+	return fmt.Sprintf("%#x", uint32(l))
+}
+
+// Imm represents an immediate number.
+type Imm int32
+
+func (Imm) IsArg() {}
+func (i Imm) String() string {
+	return fmt.Sprintf("%d", int32(i))
+}
+
+// Offset represents a memory offset immediate.
+type Offset int32
+
+func (Offset) IsArg() {}
+func (o Offset) String() string {
+	return fmt.Sprintf("%+d", int32(o))
+}

vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go

@@ -0,0 +1,172 @@
+// Copyright 2015 The Go Authors.  All rights reserved.
+// Use of this source code is governed by a BSD-style
+// license that can be found in the LICENSE file.
+
+package ppc64asm
+
+import (
+	"fmt"
+	"strings"
+)
+
+// GoSyntax returns the Go assembler syntax for the instruction.
+// The pc is the program counter of the first instruction, used for expanding
+// PC-relative addresses into absolute ones.
+// The symname function queries the symbol table for the program
+// being disassembled. It returns the name and base address of the symbol
+// containing the target, if any; otherwise it returns "", 0.
+func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) string {
+	if symname == nil {
+		symname = func(uint64) (string, uint64) { return "", 0 }
+	}
+	if inst.Op == 0 {
+		return "?"
+	}
+	var args []string
+	for i, a := range inst.Args[:] {
+		if a == nil {
+			break
+		}
+		if s := plan9Arg(&inst, i, pc, a, symname); s != "" {
+			args = append(args, s)
+		}
+	}
+	var op string
+	op = plan9OpMap[inst.Op]
+	if op == "" {
+		op = strings.ToUpper(inst.Op.String())
+	}
+	// laid out the instruction
+	switch inst.Op {
+	default: // dst, sA, sB, ...
+		if len(args) == 0 {
+			return op
+		} else if len(args) == 1 {
+			return fmt.Sprintf("%s %s", op, args[0])
+		}
+		args = append(args, args[0])
+		return op + " " + strings.Join(args[1:], ", ")
+	// store instructions always have the memory operand at the end, no need to reorder
+	case STB, STBU, STBX, STBUX,
+		STH, STHU, STHX, STHUX,
+		STW, STWU, STWX, STWUX,
+		STD, STDU, STDX, STDUX,
+		STQ,
+		STHBRX, STWBRX:
+		return op + " " + strings.Join(args, ", ")
+	// branch instructions needs additional handling
+	case BCLR:
+		if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
+			return "RET"
+		}
+		return op + " " + strings.Join(args, ", ")
+	case BC:
+		if int(inst.Args[0].(Imm))&0x1c == 12 { // jump on cond bit set
+			return fmt.Sprintf("B%s %s", args[1], args[2])
+		} else if int(inst.Args[0].(Imm))&0x1c == 4 && revCondMap[args[1]] != "" { // jump on cond bit not set
+			return fmt.Sprintf("B%s %s", revCondMap[args[1]], args[2])
+		}
+		return op + " " + strings.Join(args, ", ")
+	case BCCTR:
+		if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
+			return "BR (CTR)"
+		}
+		return op + " " + strings.Join(args, ", ")
+	case BCCTRL:
+		if int(inst.Args[0].(Imm))&20 == 20 { // unconditional
+			return "BL (CTR)"
+		}
+		return op + " " + strings.Join(args, ", ")
+	case BCA, BCL, BCLA, BCLRL, BCTAR, BCTARL:
+		return op + " " + strings.Join(args, ", ")
+	}
+}
+
+// plan9Arg formats arg (which is the argIndex's arg in inst) according to Plan 9 rules.
+// NOTE: because Plan9Syntax is the only caller of this func, and it receives a copy
+//       of inst, it's ok to modify inst.Args here.
+func plan9Arg(inst *Inst, argIndex int, pc uint64, arg Arg, symname func(uint64) (string, uint64)) string {
+	// special cases for load/store instructions
+	if _, ok := arg.(Offset); ok {
+		if argIndex+1 == len(inst.Args) || inst.Args[argIndex+1] == nil {
+			panic(fmt.Errorf("wrong table: offset not followed by register"))
+		}
+	}
+	switch arg := arg.(type) {
+	case Reg:
+		if isLoadStoreOp(inst.Op) && argIndex == 1 && arg == R0 {
+			return "0"
+		}
+		if arg == R30 {
+			return "g"
+		}
+		return strings.ToUpper(arg.String())
+	case CondReg:
+		if arg == CR0 && strings.HasPrefix(inst.Op.String(), "cmp") {
+			return "" // don't show cr0 for cmp instructions
+		} else if arg >= CR0 {
+			return fmt.Sprintf("CR%d", int(arg-CR0))
+		}
+		bit := [4]string{"LT", "GT", "EQ", "SO"}[(arg-Cond0LT)%4]
+		if arg <= Cond0SO {
+			return bit
+		}
+		return fmt.Sprintf("4*CR%d+%s", int(arg-Cond0LT)/4, bit)
+	case Imm:
+		return fmt.Sprintf("$%d", arg)
+	case SpReg:
+		switch arg {
+		case 8:
+			return "LR"
+		case 9:
+			return "CTR"
+		}
+		return fmt.Sprintf("SPR(%d)", int(arg))
+	case PCRel:
+		addr := pc + uint64(int64(arg))
+		if s, base := symname(addr); s != "" && base == addr {
+			return fmt.Sprintf("%s(SB)", s)
+		}
+		return fmt.Sprintf("%#x", addr)
+	case Label:
+		return fmt.Sprintf("%#x", int(arg))
+	case Offset:
+		reg := inst.Args[argIndex+1].(Reg)
+		removeArg(inst, argIndex+1)
+		if reg == R0 {
+			return fmt.Sprintf("%d(0)", int(arg))
+		}
+		return fmt.Sprintf("%d(R%d)", int(arg), reg-R0)
+	}
+	return fmt.Sprintf("???(%v)", arg)
+}
+
+// revCondMap maps a conditional register bit to its inverse, if possible.
+var revCondMap = map[string]string{
+	"LT": "GE", "GT": "LE", "EQ": "NE",
+}
+
+// plan9OpMap maps an Op to its Plan 9 mnemonics, if different than its GNU mnemonics.
+var plan9OpMap = map[Op]string{
+	LWARX: "LWAR", STWCX_: "STWCCC",
+	LDARX: "LDAR", STDCX_: "STDCCC",
+	LHARX: "LHAR", STHCX_: "STHCCC",
+	LBARX: "LBAR", STBCX_: "STBCCC",
+	ADDI: "ADD",
+	ADD_: "ADDCC",
+	LBZ:  "MOVBZ", STB: "MOVB",
+	LBZU: "MOVBZU", STBU: "MOVBU", // TODO(minux): indexed forms are not handled
+	LHZ: "MOVHZ", LHA: "MOVH", STH: "MOVH",
+	LHZU: "MOVHZU", STHU: "MOVHU",
+	LI:  "MOVD",
+	LIS: "ADDIS",
+	LWZ: "MOVWZ", LWA: "MOVW", STW: "MOVW",
+	LWZU: "MOVWZU", STWU: "MOVWU",
+	LD: "MOVD", STD: "MOVD",
+	LDU: "MOVDU", STDU: "MOVDU",
+	MTSPR: "MOVD", MFSPR: "MOVD", // the width is ambiguous for SPRs
+	B:     "BR",
+	BL:    "CALL",
+	CMPLD: "CMPU", CMPLW: "CMPWU",
+	CMPD: "CMP", CMPW: "CMPW",
+}