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720 lines
10 KiB
Go
720 lines
10 KiB
Go
// cmd/7c/7.out.h from Vita Nuova.
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// https://code.google.com/p/ken-cc/source/browse/src/cmd/7c/7.out.h
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package arm64
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import "github.com/google/gops/internal/obj"
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const (
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NSNAME = 8
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NSYM = 50
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NREG = 32 /* number of general registers */
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NFREG = 32 /* number of floating point registers */
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)
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// General purpose registers, kept in the low bits of Prog.Reg.
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const (
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// integer
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REG_R0 = obj.RBaseARM64 + iota
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REG_R1
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REG_R2
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REG_R3
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REG_R4
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REG_R5
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REG_R6
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REG_R7
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REG_R8
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REG_R9
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REG_R10
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REG_R11
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REG_R12
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REG_R13
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REG_R14
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REG_R15
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REG_R16
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REG_R17
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REG_R18
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REG_R19
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REG_R20
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REG_R21
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REG_R22
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REG_R23
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REG_R24
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REG_R25
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REG_R26
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REG_R27
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REG_R28
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REG_R29
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REG_R30
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REG_R31
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// scalar floating point
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REG_F0
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REG_F1
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REG_F2
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REG_F3
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REG_F4
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REG_F5
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REG_F6
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REG_F7
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REG_F8
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REG_F9
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REG_F10
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REG_F11
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REG_F12
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REG_F13
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REG_F14
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REG_F15
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REG_F16
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REG_F17
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REG_F18
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REG_F19
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REG_F20
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REG_F21
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REG_F22
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REG_F23
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REG_F24
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REG_F25
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REG_F26
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REG_F27
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REG_F28
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REG_F29
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REG_F30
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REG_F31
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// SIMD
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REG_V0
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REG_V1
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REG_V2
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REG_V3
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REG_V4
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REG_V5
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REG_V6
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REG_V7
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REG_V8
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REG_V9
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REG_V10
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REG_V11
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REG_V12
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REG_V13
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REG_V14
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REG_V15
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REG_V16
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REG_V17
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REG_V18
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REG_V19
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REG_V20
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REG_V21
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REG_V22
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REG_V23
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REG_V24
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REG_V25
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REG_V26
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REG_V27
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REG_V28
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REG_V29
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REG_V30
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REG_V31
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// The EQ in
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// CSET EQ, R0
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// is encoded as TYPE_REG, even though it's not really a register.
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COND_EQ
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COND_NE
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COND_HS
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COND_LO
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COND_MI
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COND_PL
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COND_VS
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COND_VC
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COND_HI
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COND_LS
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COND_GE
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COND_LT
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COND_GT
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COND_LE
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COND_AL
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COND_NV
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REG_RSP = REG_V31 + 32 // to differentiate ZR/SP, REG_RSP&0x1f = 31
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)
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// Not registers, but flags that can be combined with regular register
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// constants to indicate extended register conversion. When checking,
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// you should subtract obj.RBaseARM64 first. From this difference, bit 11
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// indicates extended register, bits 8-10 select the conversion mode.
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const REG_EXT = obj.RBaseARM64 + 1<<11
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const (
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REG_UXTB = REG_EXT + iota<<8
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REG_UXTH
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REG_UXTW
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REG_UXTX
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REG_SXTB
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REG_SXTH
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REG_SXTW
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REG_SXTX
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)
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// Special registers, after subtracting obj.RBaseARM64, bit 12 indicates
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// a special register and the low bits select the register.
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const (
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REG_SPECIAL = obj.RBaseARM64 + 1<<12 + iota
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REG_DAIF
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REG_NZCV
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REG_FPSR
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REG_FPCR
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REG_SPSR_EL1
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REG_ELR_EL1
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REG_SPSR_EL2
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REG_ELR_EL2
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REG_CurrentEL
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REG_SP_EL0
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REG_SPSel
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REG_DAIFSet
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REG_DAIFClr
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)
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// Register assignments:
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//
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// compiler allocates R0 up as temps
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// compiler allocates register variables R7-R25
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// compiler allocates external registers R26 down
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//
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// compiler allocates register variables F7-F26
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// compiler allocates external registers F26 down
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const (
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REGMIN = REG_R7 // register variables allocated from here to REGMAX
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REGRT1 = REG_R16 // ARM64 IP0, for external linker, runtime, duffzero and duffcopy
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REGRT2 = REG_R17 // ARM64 IP1, for external linker, runtime, duffcopy
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REGPR = REG_R18 // ARM64 platform register, unused in the Go toolchain
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REGMAX = REG_R25
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REGCTXT = REG_R26 // environment for closures
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REGTMP = REG_R27 // reserved for liblink
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REGG = REG_R28 // G
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REGFP = REG_R29 // frame pointer, unused in the Go toolchain
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REGLINK = REG_R30
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// ARM64 uses R31 as both stack pointer and zero register,
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// depending on the instruction. To differentiate RSP from ZR,
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// we use a different numeric value for REGZERO and REGSP.
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REGZERO = REG_R31
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REGSP = REG_RSP
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FREGRET = REG_F0
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FREGMIN = REG_F7 // first register variable
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FREGMAX = REG_F26 // last register variable for 7g only
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FREGEXT = REG_F26 // first external register
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)
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const (
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BIG = 2048 - 8
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)
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const (
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/* mark flags */
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LABEL = 1 << iota
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LEAF
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FLOAT
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BRANCH
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LOAD
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FCMP
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SYNC
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LIST
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FOLL
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NOSCHED
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)
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const (
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C_NONE = iota
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C_REG // R0..R30
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C_RSP // R0..R30, RSP
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C_FREG // F0..F31
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C_VREG // V0..V31
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C_PAIR // (Rn, Rm)
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C_SHIFT // Rn<<2
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C_EXTREG // Rn.UXTB<<3
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C_SPR // REG_NZCV
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C_COND // EQ, NE, etc
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C_ZCON // $0 or ZR
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C_ADDCON0 // 12-bit unsigned, unshifted
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C_ADDCON // 12-bit unsigned, shifted left by 0 or 12
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C_MOVCON // generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16
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C_BITCON // bitfield and logical immediate masks
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C_ABCON0 // could be C_ADDCON0 or C_BITCON
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C_ABCON // could be C_ADDCON or C_BITCON
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C_MBCON // could be C_MOVCON or C_BITCON
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C_LCON // 32-bit constant
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C_VCON // 64-bit constant
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C_FCON // floating-point constant
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C_VCONADDR // 64-bit memory address
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C_AACON // ADDCON offset in auto constant $a(FP)
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C_LACON // 32-bit offset in auto constant $a(FP)
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C_AECON // ADDCON offset in extern constant $e(SB)
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// TODO(aram): only one branch class should be enough
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C_SBRA // for TYPE_BRANCH
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C_LBRA
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C_NPAUTO // -512 <= x < 0, 0 mod 8
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C_NSAUTO // -256 <= x < 0
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C_PSAUTO // 0 to 255
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C_PPAUTO // 0 to 504, 0 mod 8
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C_UAUTO4K // 0 to 4095
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C_UAUTO8K // 0 to 8190, 0 mod 2
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C_UAUTO16K // 0 to 16380, 0 mod 4
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C_UAUTO32K // 0 to 32760, 0 mod 8
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C_UAUTO64K // 0 to 65520, 0 mod 16
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C_LAUTO // any other 32-bit constant
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C_SEXT1 // 0 to 4095, direct
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C_SEXT2 // 0 to 8190
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C_SEXT4 // 0 to 16380
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C_SEXT8 // 0 to 32760
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C_SEXT16 // 0 to 65520
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C_LEXT
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// TODO(aram): s/AUTO/INDIR/
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C_ZOREG // 0(R)
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C_NPOREG // mirror NPAUTO, etc
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C_NSOREG
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C_PSOREG
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C_PPOREG
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C_UOREG4K
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C_UOREG8K
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C_UOREG16K
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C_UOREG32K
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C_UOREG64K
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C_LOREG
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C_ADDR // TODO(aram): explain difference from C_VCONADDR
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// The GOT slot for a symbol in -dynlink mode.
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C_GOTADDR
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// TLS "var" in local exec mode: will become a constant offset from
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// thread local base that is ultimately chosen by the program linker.
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C_TLS_LE
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// TLS "var" in initial exec mode: will become a memory address (chosen
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// by the program linker) that the dynamic linker will fill with the
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// offset from the thread local base.
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C_TLS_IE
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C_ROFF // register offset (including register extended)
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C_GOK
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C_TEXTSIZE
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C_NCLASS // must be last
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)
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const (
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C_XPRE = 1 << 6 // match arm.C_WBIT, so Prog.String know how to print it
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C_XPOST = 1 << 5 // match arm.C_PBIT, so Prog.String know how to print it
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)
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//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm64
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const (
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AADC = obj.ABaseARM64 + obj.A_ARCHSPECIFIC + iota
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AADCS
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AADCSW
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AADCW
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AADD
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AADDS
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AADDSW
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AADDW
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AADR
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AADRP
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AAND
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AANDS
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AANDSW
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AANDW
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AASR
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AASRW
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AAT
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ABFI
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ABFIW
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ABFM
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ABFMW
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ABFXIL
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ABFXILW
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ABIC
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ABICS
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ABICSW
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ABICW
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ABRK
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ACBNZ
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ACBNZW
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ACBZ
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ACBZW
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ACCMN
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ACCMNW
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ACCMP
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ACCMPW
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ACINC
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ACINCW
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ACINV
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ACINVW
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ACLREX
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ACLS
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ACLSW
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ACLZ
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ACLZW
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ACMN
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ACMNW
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ACMP
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ACMPW
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ACNEG
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ACNEGW
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ACRC32B
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ACRC32CB
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ACRC32CH
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ACRC32CW
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ACRC32CX
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ACRC32H
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ACRC32W
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ACRC32X
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ACSEL
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ACSELW
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ACSET
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ACSETM
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ACSETMW
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ACSETW
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ACSINC
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ACSINCW
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ACSINV
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ACSINVW
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ACSNEG
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ACSNEGW
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ADC
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ADCPS1
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ADCPS2
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ADCPS3
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ADMB
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ADRPS
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ADSB
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AEON
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AEONW
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AEOR
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AEORW
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AERET
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AEXTR
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AEXTRW
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AHINT
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AHLT
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AHVC
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AIC
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AISB
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ALDAR
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ALDARB
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ALDARH
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ALDARW
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ALDAXP
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ALDAXPW
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ALDAXR
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ALDAXRB
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ALDAXRH
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ALDAXRW
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ALDP
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ALDXR
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ALDXRB
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ALDXRH
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ALDXRW
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ALDXP
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ALDXPW
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ALSL
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ALSLW
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ALSR
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ALSRW
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AMADD
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AMADDW
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AMNEG
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AMNEGW
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AMOVK
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AMOVKW
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AMOVN
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AMOVNW
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AMOVZ
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AMOVZW
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AMRS
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AMSR
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AMSUB
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AMSUBW
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AMUL
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AMULW
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AMVN
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AMVNW
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ANEG
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ANEGS
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ANEGSW
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ANEGW
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ANGC
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ANGCS
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ANGCSW
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ANGCW
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AORN
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AORNW
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AORR
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AORRW
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APRFM
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APRFUM
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ARBIT
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ARBITW
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AREM
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AREMW
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AREV
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AREV16
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AREV16W
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AREV32
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AREVW
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AROR
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ARORW
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ASBC
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ASBCS
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ASBCSW
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ASBCW
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ASBFIZ
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ASBFIZW
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ASBFM
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ASBFMW
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ASBFX
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ASBFXW
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ASDIV
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ASDIVW
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ASEV
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ASEVL
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ASMADDL
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ASMC
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ASMNEGL
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ASMSUBL
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ASMULH
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ASMULL
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ASTXR
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ASTXRB
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ASTXRH
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ASTXP
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ASTXPW
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ASTXRW
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ASTLP
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ASTLPW
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ASTLR
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ASTLRB
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ASTLRH
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ASTLRW
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ASTLXP
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ASTLXPW
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ASTLXR
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ASTLXRB
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ASTLXRH
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ASTLXRW
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ASTP
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ASUB
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ASUBS
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ASUBSW
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ASUBW
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ASVC
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ASXTB
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ASXTBW
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ASXTH
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ASXTHW
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ASXTW
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ASYS
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ASYSL
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ATBNZ
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ATBZ
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ATLBI
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ATST
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ATSTW
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AUBFIZ
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AUBFIZW
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AUBFM
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AUBFMW
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AUBFX
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AUBFXW
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AUDIV
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AUDIVW
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AUMADDL
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AUMNEGL
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AUMSUBL
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AUMULH
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AUMULL
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AUREM
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AUREMW
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AUXTB
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AUXTH
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AUXTW
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AUXTBW
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AUXTHW
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AWFE
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AWFI
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AYIELD
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AMOVB
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AMOVBU
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AMOVH
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AMOVHU
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AMOVW
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AMOVWU
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AMOVD
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AMOVNP
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AMOVNPW
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AMOVP
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AMOVPD
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AMOVPQ
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AMOVPS
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AMOVPSW
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AMOVPW
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ABEQ
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ABNE
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ABCS
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ABHS
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ABCC
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ABLO
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ABMI
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ABPL
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ABVS
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ABVC
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ABHI
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ABLS
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ABGE
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ABLT
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ABGT
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ABLE
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AFABSD
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AFABSS
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AFADDD
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AFADDS
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AFCCMPD
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AFCCMPED
|
|
AFCCMPS
|
|
AFCCMPES
|
|
AFCMPD
|
|
AFCMPED
|
|
AFCMPES
|
|
AFCMPS
|
|
AFCVTSD
|
|
AFCVTDS
|
|
AFCVTZSD
|
|
AFCVTZSDW
|
|
AFCVTZSS
|
|
AFCVTZSSW
|
|
AFCVTZUD
|
|
AFCVTZUDW
|
|
AFCVTZUS
|
|
AFCVTZUSW
|
|
AFDIVD
|
|
AFDIVS
|
|
AFMOVD
|
|
AFMOVS
|
|
AFMULD
|
|
AFMULS
|
|
AFNEGD
|
|
AFNEGS
|
|
AFSQRTD
|
|
AFSQRTS
|
|
AFSUBD
|
|
AFSUBS
|
|
ASCVTFD
|
|
ASCVTFS
|
|
ASCVTFWD
|
|
ASCVTFWS
|
|
AUCVTFD
|
|
AUCVTFS
|
|
AUCVTFWD
|
|
AUCVTFWS
|
|
AWORD
|
|
ADWORD
|
|
AFCSELS
|
|
AFCSELD
|
|
AFMAXS
|
|
AFMINS
|
|
AFMAXD
|
|
AFMIND
|
|
AFMAXNMS
|
|
AFMAXNMD
|
|
AFNMULS
|
|
AFNMULD
|
|
AFRINTNS
|
|
AFRINTND
|
|
AFRINTPS
|
|
AFRINTPD
|
|
AFRINTMS
|
|
AFRINTMD
|
|
AFRINTZS
|
|
AFRINTZD
|
|
AFRINTAS
|
|
AFRINTAD
|
|
AFRINTXS
|
|
AFRINTXD
|
|
AFRINTIS
|
|
AFRINTID
|
|
AFMADDS
|
|
AFMADDD
|
|
AFMSUBS
|
|
AFMSUBD
|
|
AFNMADDS
|
|
AFNMADDD
|
|
AFNMSUBS
|
|
AFNMSUBD
|
|
AFMINNMS
|
|
AFMINNMD
|
|
AFCVTDH
|
|
AFCVTHS
|
|
AFCVTHD
|
|
AFCVTSH
|
|
AAESD
|
|
AAESE
|
|
AAESIMC
|
|
AAESMC
|
|
ASHA1C
|
|
ASHA1H
|
|
ASHA1M
|
|
ASHA1P
|
|
ASHA1SU0
|
|
ASHA1SU1
|
|
ASHA256H
|
|
ASHA256H2
|
|
ASHA256SU0
|
|
ASHA256SU1
|
|
ALAST
|
|
AB = obj.AJMP
|
|
ABL = obj.ACALL
|
|
)
|
|
|
|
const (
|
|
// shift types
|
|
SHIFT_LL = 0 << 22
|
|
SHIFT_LR = 1 << 22
|
|
SHIFT_AR = 2 << 22
|
|
)
|