mirror of
https://github.com/cwinfo/matterbridge.git
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929 lines
21 KiB
Go
929 lines
21 KiB
Go
// Copyright 2014 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package x86asm
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import (
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"fmt"
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"strings"
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)
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// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils.
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// This general form is often called ``AT&T syntax'' as a reference to AT&T System V Unix.
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func GNUSyntax(inst Inst) string {
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// Rewrite instruction to mimic GNU peculiarities.
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// Note that inst has been passed by value and contains
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// no pointers, so any changes we make here are local
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// and will not propagate back out to the caller.
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// Adjust opcode [sic].
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switch inst.Op {
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case FDIV, FDIVR, FSUB, FSUBR, FDIVP, FDIVRP, FSUBP, FSUBRP:
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// DC E0, DC F0: libopcodes swaps FSUBR/FSUB and FDIVR/FDIV, at least
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// if you believe the Intel manual is correct (the encoding is irregular as given;
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// libopcodes uses the more regular expected encoding).
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// TODO(rsc): Test to ensure Intel manuals are correct and report to libopcodes maintainers?
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// NOTE: iant thinks this is deliberate, but we can't find the history.
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_, reg1 := inst.Args[0].(Reg)
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_, reg2 := inst.Args[1].(Reg)
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if reg1 && reg2 && (inst.Opcode>>24 == 0xDC || inst.Opcode>>24 == 0xDE) {
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switch inst.Op {
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case FDIV:
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inst.Op = FDIVR
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case FDIVR:
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inst.Op = FDIV
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case FSUB:
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inst.Op = FSUBR
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case FSUBR:
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inst.Op = FSUB
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case FDIVP:
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inst.Op = FDIVRP
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case FDIVRP:
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inst.Op = FDIVP
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case FSUBP:
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inst.Op = FSUBRP
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case FSUBRP:
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inst.Op = FSUBP
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}
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}
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case MOVNTSD:
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// MOVNTSD is F2 0F 2B /r.
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// MOVNTSS is F3 0F 2B /r (supposedly; not in manuals).
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// Usually inner prefixes win for display,
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// so that F3 F2 0F 2B 11 is REP MOVNTSD
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// and F2 F3 0F 2B 11 is REPN MOVNTSS.
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// Libopcodes always prefers MOVNTSS regardless of prefix order.
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if countPrefix(&inst, 0xF3) > 0 {
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found := false
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for i := len(inst.Prefix) - 1; i >= 0; i-- {
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switch inst.Prefix[i] & 0xFF {
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case 0xF3:
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if !found {
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found = true
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inst.Prefix[i] |= PrefixImplicit
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}
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case 0xF2:
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inst.Prefix[i] &^= PrefixImplicit
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}
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}
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inst.Op = MOVNTSS
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}
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}
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// Add implicit arguments.
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switch inst.Op {
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case MONITOR:
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inst.Args[0] = EDX
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inst.Args[1] = ECX
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inst.Args[2] = EAX
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if inst.AddrSize == 16 {
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inst.Args[2] = AX
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}
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case MWAIT:
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if inst.Mode == 64 {
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inst.Args[0] = RCX
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inst.Args[1] = RAX
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} else {
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inst.Args[0] = ECX
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inst.Args[1] = EAX
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}
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}
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// Adjust which prefixes will be displayed.
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// The rule is to display all the prefixes not implied by
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// the usual instruction display, that is, all the prefixes
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// except the ones with PrefixImplicit set.
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// However, of course, there are exceptions to the rule.
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switch inst.Op {
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case CRC32:
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// CRC32 has a mandatory F2 prefix.
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// If there are multiple F2s and no F3s, the extra F2s do not print.
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// (And Decode has already marked them implicit.)
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// However, if there is an F3 anywhere, then the extra F2s do print.
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// If there are multiple F2 prefixes *and* an (ignored) F3,
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// then libopcodes prints the extra F2s as REPNs.
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if countPrefix(&inst, 0xF2) > 1 {
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unmarkImplicit(&inst, 0xF2)
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markLastImplicit(&inst, 0xF2)
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}
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// An unused data size override should probably be shown,
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// to distinguish DATA16 CRC32B from plain CRC32B,
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// but libopcodes always treats the final override as implicit
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// and the others as explicit.
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unmarkImplicit(&inst, PrefixDataSize)
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markLastImplicit(&inst, PrefixDataSize)
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case CVTSI2SD, CVTSI2SS:
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if !isMem(inst.Args[1]) {
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markLastImplicit(&inst, PrefixDataSize)
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}
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case CVTSD2SI, CVTSS2SI, CVTTSD2SI, CVTTSS2SI,
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ENTER, FLDENV, FNSAVE, FNSTENV, FRSTOR, LGDT, LIDT, LRET,
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POP, PUSH, RET, SGDT, SIDT, SYSRET, XBEGIN:
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markLastImplicit(&inst, PrefixDataSize)
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case LOOP, LOOPE, LOOPNE, MONITOR:
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markLastImplicit(&inst, PrefixAddrSize)
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case MOV:
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// The 16-bit and 32-bit forms of MOV Sreg, dst and MOV src, Sreg
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// cannot be distinguished when src or dst refers to memory, because
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// Sreg is always a 16-bit value, even when we're doing a 32-bit
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// instruction. Because the instruction tables distinguished these two,
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// any operand size prefix has been marked as used (to decide which
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// branch to take). Unmark it, so that it will show up in disassembly,
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// so that the reader can tell the size of memory operand.
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// up with the same arguments
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dst, _ := inst.Args[0].(Reg)
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src, _ := inst.Args[1].(Reg)
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if ES <= src && src <= GS && isMem(inst.Args[0]) || ES <= dst && dst <= GS && isMem(inst.Args[1]) {
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unmarkImplicit(&inst, PrefixDataSize)
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}
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case MOVDQU:
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if countPrefix(&inst, 0xF3) > 1 {
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unmarkImplicit(&inst, 0xF3)
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markLastImplicit(&inst, 0xF3)
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}
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case MOVQ2DQ:
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markLastImplicit(&inst, PrefixDataSize)
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case SLDT, SMSW, STR, FXRSTOR, XRSTOR, XSAVE, XSAVEOPT, CMPXCHG8B:
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if isMem(inst.Args[0]) {
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unmarkImplicit(&inst, PrefixDataSize)
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}
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case SYSEXIT:
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unmarkImplicit(&inst, PrefixDataSize)
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}
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if isCondJmp[inst.Op] || isLoop[inst.Op] || inst.Op == JCXZ || inst.Op == JECXZ || inst.Op == JRCXZ {
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if countPrefix(&inst, PrefixCS) > 0 && countPrefix(&inst, PrefixDS) > 0 {
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for i, p := range inst.Prefix {
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switch p & 0xFFF {
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case PrefixPN, PrefixPT:
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inst.Prefix[i] &= 0xF0FF // cut interpretation bits, producing original segment prefix
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}
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}
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}
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}
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// XACQUIRE/XRELEASE adjustment.
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if inst.Op == MOV {
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// MOV into memory is a candidate for turning REP into XRELEASE.
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// However, if the REP is followed by a REPN, that REPN blocks the
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// conversion.
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haveREPN := false
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for i := len(inst.Prefix) - 1; i >= 0; i-- {
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switch inst.Prefix[i] &^ PrefixIgnored {
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case PrefixREPN:
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haveREPN = true
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case PrefixXRELEASE:
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if haveREPN {
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inst.Prefix[i] = PrefixREP
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}
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}
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}
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}
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// We only format the final F2/F3 as XRELEASE/XACQUIRE.
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haveXA := false
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haveXR := false
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for i := len(inst.Prefix) - 1; i >= 0; i-- {
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switch inst.Prefix[i] &^ PrefixIgnored {
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case PrefixXRELEASE:
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if !haveXR {
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haveXR = true
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} else {
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inst.Prefix[i] = PrefixREP
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}
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case PrefixXACQUIRE:
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if !haveXA {
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haveXA = true
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} else {
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inst.Prefix[i] = PrefixREPN
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}
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}
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}
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// Determine opcode.
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op := strings.ToLower(inst.Op.String())
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if alt := gnuOp[inst.Op]; alt != "" {
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op = alt
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}
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// Determine opcode suffix.
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// Libopcodes omits the suffix if the width of the operation
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// can be inferred from a register arguments. For example,
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// add $1, %ebx has no suffix because you can tell from the
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// 32-bit register destination that it is a 32-bit add,
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// but in addl $1, (%ebx), the destination is memory, so the
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// size is not evident without the l suffix.
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needSuffix := true
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SuffixLoop:
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for i, a := range inst.Args {
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if a == nil {
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break
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}
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switch a := a.(type) {
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case Reg:
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switch inst.Op {
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case MOVSX, MOVZX:
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continue
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case SHL, SHR, RCL, RCR, ROL, ROR, SAR:
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if i == 1 {
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// shift count does not tell us operand size
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continue
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}
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case CRC32:
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// The source argument does tell us operand size,
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// but libopcodes still always puts a suffix on crc32.
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continue
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case PUSH, POP:
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// Even though segment registers are 16-bit, push and pop
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// can save/restore them from 32-bit slots, so they
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// do not imply operand size.
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if ES <= a && a <= GS {
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continue
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}
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case CVTSI2SD, CVTSI2SS:
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// The integer register argument takes priority.
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if X0 <= a && a <= X15 {
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continue
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}
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}
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if AL <= a && a <= R15 || ES <= a && a <= GS || X0 <= a && a <= X15 || M0 <= a && a <= M7 {
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needSuffix = false
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break SuffixLoop
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}
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}
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}
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if needSuffix {
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switch inst.Op {
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case CMPXCHG8B, FLDCW, FNSTCW, FNSTSW, LDMXCSR, LLDT, LMSW, LTR, PCLMULQDQ,
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SETA, SETAE, SETB, SETBE, SETE, SETG, SETGE, SETL, SETLE, SETNE, SETNO, SETNP, SETNS, SETO, SETP, SETS,
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SLDT, SMSW, STMXCSR, STR, VERR, VERW:
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// For various reasons, libopcodes emits no suffix for these instructions.
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case CRC32:
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op += byteSizeSuffix(argBytes(&inst, inst.Args[1]))
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case LGDT, LIDT, SGDT, SIDT:
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op += byteSizeSuffix(inst.DataSize / 8)
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case MOVZX, MOVSX:
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// Integer size conversions get two suffixes.
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op = op[:4] + byteSizeSuffix(argBytes(&inst, inst.Args[1])) + byteSizeSuffix(argBytes(&inst, inst.Args[0]))
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case LOOP, LOOPE, LOOPNE:
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// Add w suffix to indicate use of CX register instead of ECX.
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if inst.AddrSize == 16 {
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op += "w"
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}
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case CALL, ENTER, JMP, LCALL, LEAVE, LJMP, LRET, RET, SYSRET, XBEGIN:
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// Add w suffix to indicate use of 16-bit target.
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// Exclude JMP rel8.
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if inst.Opcode>>24 == 0xEB {
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break
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}
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if inst.DataSize == 16 && inst.Mode != 16 {
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markLastImplicit(&inst, PrefixDataSize)
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op += "w"
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} else if inst.Mode == 64 {
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op += "q"
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}
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case FRSTOR, FNSAVE, FNSTENV, FLDENV:
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// Add s suffix to indicate shortened FPU state (I guess).
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if inst.DataSize == 16 {
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op += "s"
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}
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case PUSH, POP:
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if markLastImplicit(&inst, PrefixDataSize) {
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op += byteSizeSuffix(inst.DataSize / 8)
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} else if inst.Mode == 64 {
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op += "q"
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} else {
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op += byteSizeSuffix(inst.MemBytes)
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}
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default:
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if isFloat(inst.Op) {
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// I can't explain any of this, but it's what libopcodes does.
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switch inst.MemBytes {
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default:
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if (inst.Op == FLD || inst.Op == FSTP) && isMem(inst.Args[0]) {
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op += "t"
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}
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case 4:
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if isFloatInt(inst.Op) {
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op += "l"
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} else {
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op += "s"
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}
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case 8:
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if isFloatInt(inst.Op) {
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op += "ll"
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} else {
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op += "l"
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}
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}
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break
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}
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op += byteSizeSuffix(inst.MemBytes)
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}
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}
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// Adjust special case opcodes.
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switch inst.Op {
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case 0:
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if inst.Prefix[0] != 0 {
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return strings.ToLower(inst.Prefix[0].String())
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}
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case INT:
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if inst.Opcode>>24 == 0xCC {
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inst.Args[0] = nil
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op = "int3"
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}
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case CMPPS, CMPPD, CMPSD_XMM, CMPSS:
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imm, ok := inst.Args[2].(Imm)
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if ok && 0 <= imm && imm < 8 {
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inst.Args[2] = nil
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op = cmppsOps[imm] + op[3:]
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}
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case PCLMULQDQ:
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imm, ok := inst.Args[2].(Imm)
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if ok && imm&^0x11 == 0 {
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inst.Args[2] = nil
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op = pclmulqOps[(imm&0x10)>>3|(imm&1)]
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}
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case XLATB:
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if markLastImplicit(&inst, PrefixAddrSize) {
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op = "xlat" // not xlatb
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}
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}
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// Build list of argument strings.
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var (
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usedPrefixes bool // segment prefixes consumed by Mem formatting
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args []string // formatted arguments
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)
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for i, a := range inst.Args {
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if a == nil {
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break
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}
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switch inst.Op {
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case MOVSB, MOVSW, MOVSD, MOVSQ, OUTSB, OUTSW, OUTSD:
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if i == 0 {
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usedPrefixes = true // disable use of prefixes for first argument
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} else {
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usedPrefixes = false
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}
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}
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if a == Imm(1) && (inst.Opcode>>24)&^1 == 0xD0 {
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continue
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}
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args = append(args, gnuArg(&inst, a, &usedPrefixes))
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}
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// The default is to print the arguments in reverse Intel order.
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// A few instructions inhibit this behavior.
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switch inst.Op {
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case BOUND, LCALL, ENTER, LJMP:
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// no reverse
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default:
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// reverse args
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for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 {
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args[i], args[j] = args[j], args[i]
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}
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}
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// Build prefix string.
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// Must be after argument formatting, which can turn off segment prefixes.
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var (
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prefix = "" // output string
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numAddr = 0
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numData = 0
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implicitData = false
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)
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for _, p := range inst.Prefix {
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if p&0xFF == PrefixDataSize && p&PrefixImplicit != 0 {
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implicitData = true
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}
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}
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for _, p := range inst.Prefix {
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if p == 0 || p.IsVEX() {
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break
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}
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if p&PrefixImplicit != 0 {
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continue
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}
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switch p &^ (PrefixIgnored | PrefixInvalid) {
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default:
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if p.IsREX() {
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if p&0xFF == PrefixREX {
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prefix += "rex "
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} else {
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prefix += "rex." + p.String()[4:] + " "
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}
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break
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}
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prefix += strings.ToLower(p.String()) + " "
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case PrefixPN:
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op += ",pn"
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continue
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case PrefixPT:
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op += ",pt"
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continue
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case PrefixAddrSize, PrefixAddr16, PrefixAddr32:
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// For unknown reasons, if the addr16 prefix is repeated,
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// libopcodes displays all but the last as addr32, even though
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// the addressing form used in a memory reference is clearly
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// still 16-bit.
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n := 32
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if inst.Mode == 32 {
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n = 16
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}
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numAddr++
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if countPrefix(&inst, PrefixAddrSize) > numAddr {
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n = inst.Mode
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}
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prefix += fmt.Sprintf("addr%d ", n)
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continue
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case PrefixData16, PrefixData32:
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if implicitData && countPrefix(&inst, PrefixDataSize) > 1 {
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// Similar to the addr32 logic above, but it only kicks in
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// when something used the data size prefix (one is implicit).
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n := 16
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if inst.Mode == 16 {
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n = 32
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}
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numData++
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if countPrefix(&inst, PrefixDataSize) > numData {
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if inst.Mode == 16 {
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n = 16
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} else {
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n = 32
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}
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}
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prefix += fmt.Sprintf("data%d ", n)
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continue
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}
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prefix += strings.ToLower(p.String()) + " "
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}
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}
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// Finally! Put it all together.
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text := prefix + op
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if args != nil {
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text += " "
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// Indirect call/jmp gets a star to distinguish from direct jump address.
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if (inst.Op == CALL || inst.Op == JMP || inst.Op == LJMP || inst.Op == LCALL) && (isMem(inst.Args[0]) || isReg(inst.Args[0])) {
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text += "*"
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}
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text += strings.Join(args, ",")
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}
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return text
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}
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// gnuArg returns the GNU syntax for the argument x from the instruction inst.
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// If *usedPrefixes is false and x is a Mem, then the formatting
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// includes any segment prefixes and sets *usedPrefixes to true.
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func gnuArg(inst *Inst, x Arg, usedPrefixes *bool) string {
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if x == nil {
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return "<nil>"
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}
|
|
switch x := x.(type) {
|
|
case Reg:
|
|
switch inst.Op {
|
|
case CVTSI2SS, CVTSI2SD, CVTSS2SI, CVTSD2SI, CVTTSD2SI, CVTTSS2SI:
|
|
if inst.DataSize == 16 && EAX <= x && x <= R15L {
|
|
x -= EAX - AX
|
|
}
|
|
|
|
case IN, INSB, INSW, INSD, OUT, OUTSB, OUTSW, OUTSD:
|
|
// DX is the port, but libopcodes prints it as if it were a memory reference.
|
|
if x == DX {
|
|
return "(%dx)"
|
|
}
|
|
case VMOVDQA, VMOVDQU, VMOVNTDQA, VMOVNTDQ:
|
|
return strings.Replace(gccRegName[x], "xmm", "ymm", -1)
|
|
}
|
|
return gccRegName[x]
|
|
case Mem:
|
|
seg := ""
|
|
var haveCS, haveDS, haveES, haveFS, haveGS, haveSS bool
|
|
switch x.Segment {
|
|
case CS:
|
|
haveCS = true
|
|
case DS:
|
|
haveDS = true
|
|
case ES:
|
|
haveES = true
|
|
case FS:
|
|
haveFS = true
|
|
case GS:
|
|
haveGS = true
|
|
case SS:
|
|
haveSS = true
|
|
}
|
|
switch inst.Op {
|
|
case INSB, INSW, INSD, STOSB, STOSW, STOSD, STOSQ, SCASB, SCASW, SCASD, SCASQ:
|
|
// These do not accept segment prefixes, at least in the GNU rendering.
|
|
default:
|
|
if *usedPrefixes {
|
|
break
|
|
}
|
|
for i := len(inst.Prefix) - 1; i >= 0; i-- {
|
|
p := inst.Prefix[i] &^ PrefixIgnored
|
|
if p == 0 {
|
|
continue
|
|
}
|
|
switch p {
|
|
case PrefixCS:
|
|
if !haveCS {
|
|
haveCS = true
|
|
inst.Prefix[i] |= PrefixImplicit
|
|
}
|
|
case PrefixDS:
|
|
if !haveDS {
|
|
haveDS = true
|
|
inst.Prefix[i] |= PrefixImplicit
|
|
}
|
|
case PrefixES:
|
|
if !haveES {
|
|
haveES = true
|
|
inst.Prefix[i] |= PrefixImplicit
|
|
}
|
|
case PrefixFS:
|
|
if !haveFS {
|
|
haveFS = true
|
|
inst.Prefix[i] |= PrefixImplicit
|
|
}
|
|
case PrefixGS:
|
|
if !haveGS {
|
|
haveGS = true
|
|
inst.Prefix[i] |= PrefixImplicit
|
|
}
|
|
case PrefixSS:
|
|
if !haveSS {
|
|
haveSS = true
|
|
inst.Prefix[i] |= PrefixImplicit
|
|
}
|
|
}
|
|
}
|
|
*usedPrefixes = true
|
|
}
|
|
if haveCS {
|
|
seg += "%cs:"
|
|
}
|
|
if haveDS {
|
|
seg += "%ds:"
|
|
}
|
|
if haveSS {
|
|
seg += "%ss:"
|
|
}
|
|
if haveES {
|
|
seg += "%es:"
|
|
}
|
|
if haveFS {
|
|
seg += "%fs:"
|
|
}
|
|
if haveGS {
|
|
seg += "%gs:"
|
|
}
|
|
disp := ""
|
|
if x.Disp != 0 {
|
|
disp = fmt.Sprintf("%#x", x.Disp)
|
|
}
|
|
if x.Scale == 0 || x.Index == 0 && x.Scale == 1 && (x.Base == ESP || x.Base == RSP || x.Base == 0 && inst.Mode == 64) {
|
|
if x.Base == 0 {
|
|
return seg + disp
|
|
}
|
|
return fmt.Sprintf("%s%s(%s)", seg, disp, gccRegName[x.Base])
|
|
}
|
|
base := gccRegName[x.Base]
|
|
if x.Base == 0 {
|
|
base = ""
|
|
}
|
|
index := gccRegName[x.Index]
|
|
if x.Index == 0 {
|
|
if inst.AddrSize == 64 {
|
|
index = "%riz"
|
|
} else {
|
|
index = "%eiz"
|
|
}
|
|
}
|
|
if AX <= x.Base && x.Base <= DI {
|
|
// 16-bit addressing - no scale
|
|
return fmt.Sprintf("%s%s(%s,%s)", seg, disp, base, index)
|
|
}
|
|
return fmt.Sprintf("%s%s(%s,%s,%d)", seg, disp, base, index, x.Scale)
|
|
case Rel:
|
|
return fmt.Sprintf(".%+#x", int32(x))
|
|
case Imm:
|
|
if inst.Mode == 32 {
|
|
return fmt.Sprintf("$%#x", uint32(x))
|
|
}
|
|
return fmt.Sprintf("$%#x", int64(x))
|
|
}
|
|
return x.String()
|
|
}
|
|
|
|
var gccRegName = [...]string{
|
|
0: "REG0",
|
|
AL: "%al",
|
|
CL: "%cl",
|
|
BL: "%bl",
|
|
DL: "%dl",
|
|
AH: "%ah",
|
|
CH: "%ch",
|
|
BH: "%bh",
|
|
DH: "%dh",
|
|
SPB: "%spl",
|
|
BPB: "%bpl",
|
|
SIB: "%sil",
|
|
DIB: "%dil",
|
|
R8B: "%r8b",
|
|
R9B: "%r9b",
|
|
R10B: "%r10b",
|
|
R11B: "%r11b",
|
|
R12B: "%r12b",
|
|
R13B: "%r13b",
|
|
R14B: "%r14b",
|
|
R15B: "%r15b",
|
|
AX: "%ax",
|
|
CX: "%cx",
|
|
BX: "%bx",
|
|
DX: "%dx",
|
|
SP: "%sp",
|
|
BP: "%bp",
|
|
SI: "%si",
|
|
DI: "%di",
|
|
R8W: "%r8w",
|
|
R9W: "%r9w",
|
|
R10W: "%r10w",
|
|
R11W: "%r11w",
|
|
R12W: "%r12w",
|
|
R13W: "%r13w",
|
|
R14W: "%r14w",
|
|
R15W: "%r15w",
|
|
EAX: "%eax",
|
|
ECX: "%ecx",
|
|
EDX: "%edx",
|
|
EBX: "%ebx",
|
|
ESP: "%esp",
|
|
EBP: "%ebp",
|
|
ESI: "%esi",
|
|
EDI: "%edi",
|
|
R8L: "%r8d",
|
|
R9L: "%r9d",
|
|
R10L: "%r10d",
|
|
R11L: "%r11d",
|
|
R12L: "%r12d",
|
|
R13L: "%r13d",
|
|
R14L: "%r14d",
|
|
R15L: "%r15d",
|
|
RAX: "%rax",
|
|
RCX: "%rcx",
|
|
RDX: "%rdx",
|
|
RBX: "%rbx",
|
|
RSP: "%rsp",
|
|
RBP: "%rbp",
|
|
RSI: "%rsi",
|
|
RDI: "%rdi",
|
|
R8: "%r8",
|
|
R9: "%r9",
|
|
R10: "%r10",
|
|
R11: "%r11",
|
|
R12: "%r12",
|
|
R13: "%r13",
|
|
R14: "%r14",
|
|
R15: "%r15",
|
|
IP: "%ip",
|
|
EIP: "%eip",
|
|
RIP: "%rip",
|
|
F0: "%st",
|
|
F1: "%st(1)",
|
|
F2: "%st(2)",
|
|
F3: "%st(3)",
|
|
F4: "%st(4)",
|
|
F5: "%st(5)",
|
|
F6: "%st(6)",
|
|
F7: "%st(7)",
|
|
M0: "%mm0",
|
|
M1: "%mm1",
|
|
M2: "%mm2",
|
|
M3: "%mm3",
|
|
M4: "%mm4",
|
|
M5: "%mm5",
|
|
M6: "%mm6",
|
|
M7: "%mm7",
|
|
X0: "%xmm0",
|
|
X1: "%xmm1",
|
|
X2: "%xmm2",
|
|
X3: "%xmm3",
|
|
X4: "%xmm4",
|
|
X5: "%xmm5",
|
|
X6: "%xmm6",
|
|
X7: "%xmm7",
|
|
X8: "%xmm8",
|
|
X9: "%xmm9",
|
|
X10: "%xmm10",
|
|
X11: "%xmm11",
|
|
X12: "%xmm12",
|
|
X13: "%xmm13",
|
|
X14: "%xmm14",
|
|
X15: "%xmm15",
|
|
CS: "%cs",
|
|
SS: "%ss",
|
|
DS: "%ds",
|
|
ES: "%es",
|
|
FS: "%fs",
|
|
GS: "%gs",
|
|
GDTR: "%gdtr",
|
|
IDTR: "%idtr",
|
|
LDTR: "%ldtr",
|
|
MSW: "%msw",
|
|
TASK: "%task",
|
|
CR0: "%cr0",
|
|
CR1: "%cr1",
|
|
CR2: "%cr2",
|
|
CR3: "%cr3",
|
|
CR4: "%cr4",
|
|
CR5: "%cr5",
|
|
CR6: "%cr6",
|
|
CR7: "%cr7",
|
|
CR8: "%cr8",
|
|
CR9: "%cr9",
|
|
CR10: "%cr10",
|
|
CR11: "%cr11",
|
|
CR12: "%cr12",
|
|
CR13: "%cr13",
|
|
CR14: "%cr14",
|
|
CR15: "%cr15",
|
|
DR0: "%db0",
|
|
DR1: "%db1",
|
|
DR2: "%db2",
|
|
DR3: "%db3",
|
|
DR4: "%db4",
|
|
DR5: "%db5",
|
|
DR6: "%db6",
|
|
DR7: "%db7",
|
|
TR0: "%tr0",
|
|
TR1: "%tr1",
|
|
TR2: "%tr2",
|
|
TR3: "%tr3",
|
|
TR4: "%tr4",
|
|
TR5: "%tr5",
|
|
TR6: "%tr6",
|
|
TR7: "%tr7",
|
|
}
|
|
|
|
var gnuOp = map[Op]string{
|
|
CBW: "cbtw",
|
|
CDQ: "cltd",
|
|
CMPSD: "cmpsl",
|
|
CMPSD_XMM: "cmpsd",
|
|
CWD: "cwtd",
|
|
CWDE: "cwtl",
|
|
CQO: "cqto",
|
|
INSD: "insl",
|
|
IRET: "iretw",
|
|
IRETD: "iret",
|
|
IRETQ: "iretq",
|
|
LODSB: "lods",
|
|
LODSD: "lods",
|
|
LODSQ: "lods",
|
|
LODSW: "lods",
|
|
MOVSD: "movsl",
|
|
MOVSD_XMM: "movsd",
|
|
OUTSD: "outsl",
|
|
POPA: "popaw",
|
|
POPAD: "popa",
|
|
POPF: "popfw",
|
|
POPFD: "popf",
|
|
PUSHA: "pushaw",
|
|
PUSHAD: "pusha",
|
|
PUSHF: "pushfw",
|
|
PUSHFD: "pushf",
|
|
SCASB: "scas",
|
|
SCASD: "scas",
|
|
SCASQ: "scas",
|
|
SCASW: "scas",
|
|
STOSB: "stos",
|
|
STOSD: "stos",
|
|
STOSQ: "stos",
|
|
STOSW: "stos",
|
|
XLATB: "xlat",
|
|
}
|
|
|
|
var cmppsOps = []string{
|
|
"cmpeq",
|
|
"cmplt",
|
|
"cmple",
|
|
"cmpunord",
|
|
"cmpneq",
|
|
"cmpnlt",
|
|
"cmpnle",
|
|
"cmpord",
|
|
}
|
|
|
|
var pclmulqOps = []string{
|
|
"pclmullqlqdq",
|
|
"pclmulhqlqdq",
|
|
"pclmullqhqdq",
|
|
"pclmulhqhqdq",
|
|
}
|
|
|
|
func countPrefix(inst *Inst, target Prefix) int {
|
|
n := 0
|
|
for _, p := range inst.Prefix {
|
|
if p&0xFF == target&0xFF {
|
|
n++
|
|
}
|
|
}
|
|
return n
|
|
}
|
|
|
|
func markLastImplicit(inst *Inst, prefix Prefix) bool {
|
|
for i := len(inst.Prefix) - 1; i >= 0; i-- {
|
|
p := inst.Prefix[i]
|
|
if p&0xFF == prefix {
|
|
inst.Prefix[i] |= PrefixImplicit
|
|
return true
|
|
}
|
|
}
|
|
return false
|
|
}
|
|
|
|
func unmarkImplicit(inst *Inst, prefix Prefix) {
|
|
for i := len(inst.Prefix) - 1; i >= 0; i-- {
|
|
p := inst.Prefix[i]
|
|
if p&0xFF == prefix {
|
|
inst.Prefix[i] &^= PrefixImplicit
|
|
}
|
|
}
|
|
}
|
|
|
|
func byteSizeSuffix(b int) string {
|
|
switch b {
|
|
case 1:
|
|
return "b"
|
|
case 2:
|
|
return "w"
|
|
case 4:
|
|
return "l"
|
|
case 8:
|
|
return "q"
|
|
}
|
|
return ""
|
|
}
|
|
|
|
func argBytes(inst *Inst, arg Arg) int {
|
|
if isMem(arg) {
|
|
return inst.MemBytes
|
|
}
|
|
return regBytes(arg)
|
|
}
|
|
|
|
func isFloat(op Op) bool {
|
|
switch op {
|
|
case FADD, FCOM, FCOMP, FDIV, FDIVR, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FIST, FISTP, FISTTP, FISUB, FISUBR, FLD, FMUL, FST, FSTP, FSUB, FSUBR:
|
|
return true
|
|
}
|
|
return false
|
|
}
|
|
|
|
func isFloatInt(op Op) bool {
|
|
switch op {
|
|
case FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FIST, FISTP, FISTTP, FISUB, FISUBR:
|
|
return true
|
|
}
|
|
return false
|
|
}
|