mirror of
https://github.com/cwinfo/matterbridge.git
synced 2024-12-26 19:05:40 +00:00
568 lines
13 KiB
Go
568 lines
13 KiB
Go
// Copyright 2014 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package armasm
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import (
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"encoding/binary"
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"fmt"
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)
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// An instFormat describes the format of an instruction encoding.
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// An instruction with 32-bit value x matches the format if x&mask == value
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// and the condition matches.
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// The condition matches if x>>28 == 0xF && value>>28==0xF
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// or if x>>28 != 0xF and value>>28 == 0.
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// If x matches the format, then the rest of the fields describe how to interpret x.
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// The opBits describe bits that should be extracted from x and added to the opcode.
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// For example opBits = 0x1234 means that the value
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// (2 bits at offset 1) followed by (4 bits at offset 3)
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// should be added to op.
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// Finally the args describe how to decode the instruction arguments.
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// args is stored as a fixed-size array; if there are fewer than len(args) arguments,
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// args[i] == 0 marks the end of the argument list.
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type instFormat struct {
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mask uint32
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value uint32
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priority int8
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op Op
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opBits uint64
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args instArgs
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}
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type instArgs [4]instArg
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var (
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errMode = fmt.Errorf("unsupported execution mode")
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errShort = fmt.Errorf("truncated instruction")
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errUnknown = fmt.Errorf("unknown instruction")
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)
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var decoderCover []bool
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// Decode decodes the leading bytes in src as a single instruction.
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func Decode(src []byte, mode Mode) (inst Inst, err error) {
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if mode != ModeARM {
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return Inst{}, errMode
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}
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if len(src) < 4 {
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return Inst{}, errShort
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}
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if decoderCover == nil {
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decoderCover = make([]bool, len(instFormats))
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}
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x := binary.LittleEndian.Uint32(src)
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// The instFormat table contains both conditional and unconditional instructions.
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// Considering only the top 4 bits, the conditional instructions use mask=0, value=0,
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// while the unconditional instructions use mask=f, value=f.
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// Prepare a version of x with the condition cleared to 0 in conditional instructions
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// and then assume mask=f during matching.
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const condMask = 0xf0000000
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xNoCond := x
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if x&condMask != condMask {
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xNoCond &^= condMask
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}
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var priority int8
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Search:
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for i := range instFormats {
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f := &instFormats[i]
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if xNoCond&(f.mask|condMask) != f.value || f.priority <= priority {
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continue
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}
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delta := uint32(0)
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deltaShift := uint(0)
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for opBits := f.opBits; opBits != 0; opBits >>= 16 {
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n := uint(opBits & 0xFF)
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off := uint((opBits >> 8) & 0xFF)
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delta |= (x >> off) & (1<<n - 1) << deltaShift
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deltaShift += n
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}
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op := f.op + Op(delta)
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// Special case: BKPT encodes with condition but cannot have one.
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if op&^15 == BKPT_EQ && op != BKPT {
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continue Search
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}
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var args Args
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for j, aop := range f.args {
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if aop == 0 {
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break
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}
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arg := decodeArg(aop, x)
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if arg == nil { // cannot decode argument
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continue Search
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}
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args[j] = arg
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}
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decoderCover[i] = true
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inst = Inst{
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Op: op,
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Args: args,
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Enc: x,
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Len: 4,
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}
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priority = f.priority
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continue Search
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}
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if inst.Op != 0 {
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return inst, nil
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}
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return Inst{}, errUnknown
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}
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// An instArg describes the encoding of a single argument.
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// In the names used for arguments, _p_ means +, _m_ means -,
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// _pm_ means ± (usually keyed by the U bit).
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// The _W suffix indicates a general addressing mode based on the P and W bits.
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// The _offset and _postindex suffixes force the given addressing mode.
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// The rest should be somewhat self-explanatory, at least given
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// the decodeArg function.
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type instArg uint8
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const (
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_ instArg = iota
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arg_APSR
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arg_FPSCR
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arg_Dn_half
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arg_R1_0
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arg_R1_12
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arg_R2_0
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arg_R2_12
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arg_R_0
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arg_R_12
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arg_R_12_nzcv
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arg_R_16
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arg_R_16_WB
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arg_R_8
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arg_R_rotate
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arg_R_shift_R
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arg_R_shift_imm
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arg_SP
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arg_Sd
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arg_Sd_Dd
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arg_Dd_Sd
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arg_Sm
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arg_Sm_Dm
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arg_Sn
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arg_Sn_Dn
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arg_const
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arg_endian
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arg_fbits
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arg_fp_0
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arg_imm24
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arg_imm5
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arg_imm5_32
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arg_imm5_nz
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arg_imm_12at8_4at0
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arg_imm_4at16_12at0
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arg_imm_vfp
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arg_label24
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arg_label24H
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arg_label_m_12
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arg_label_p_12
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arg_label_pm_12
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arg_label_pm_4_4
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arg_lsb_width
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arg_mem_R
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arg_mem_R_pm_R_W
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arg_mem_R_pm_R_postindex
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arg_mem_R_pm_R_shift_imm_W
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arg_mem_R_pm_R_shift_imm_offset
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arg_mem_R_pm_R_shift_imm_postindex
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arg_mem_R_pm_imm12_W
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arg_mem_R_pm_imm12_offset
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arg_mem_R_pm_imm12_postindex
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arg_mem_R_pm_imm8_W
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arg_mem_R_pm_imm8_postindex
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arg_mem_R_pm_imm8at0_offset
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arg_option
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arg_registers
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arg_registers1
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arg_registers2
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arg_satimm4
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arg_satimm5
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arg_satimm4m1
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arg_satimm5m1
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arg_widthm1
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)
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// decodeArg decodes the arg described by aop from the instruction bits x.
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// It returns nil if x cannot be decoded according to aop.
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func decodeArg(aop instArg, x uint32) Arg {
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switch aop {
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default:
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return nil
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case arg_APSR:
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return APSR
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case arg_FPSCR:
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return FPSCR
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case arg_R_0:
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return Reg(x & (1<<4 - 1))
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case arg_R_8:
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return Reg((x >> 8) & (1<<4 - 1))
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case arg_R_12:
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return Reg((x >> 12) & (1<<4 - 1))
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case arg_R_16:
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return Reg((x >> 16) & (1<<4 - 1))
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case arg_R_12_nzcv:
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r := Reg((x >> 12) & (1<<4 - 1))
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if r == R15 {
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return APSR_nzcv
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}
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return r
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case arg_R_16_WB:
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mode := AddrLDM
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if (x>>21)&1 != 0 {
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mode = AddrLDM_WB
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}
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return Mem{Base: Reg((x >> 16) & (1<<4 - 1)), Mode: mode}
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case arg_R_rotate:
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Rm := Reg(x & (1<<4 - 1))
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typ, count := decodeShift(x)
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// ROR #0 here means ROR #0, but decodeShift rewrites to RRX #1.
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if typ == RotateRightExt {
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return Reg(Rm)
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}
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return RegShift{Rm, typ, uint8(count)}
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case arg_R_shift_R:
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Rm := Reg(x & (1<<4 - 1))
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Rs := Reg((x >> 8) & (1<<4 - 1))
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typ := Shift((x >> 5) & (1<<2 - 1))
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return RegShiftReg{Rm, typ, Rs}
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case arg_R_shift_imm:
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Rm := Reg(x & (1<<4 - 1))
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typ, count := decodeShift(x)
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if typ == ShiftLeft && count == 0 {
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return Reg(Rm)
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}
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return RegShift{Rm, typ, uint8(count)}
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case arg_R1_0:
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return Reg((x & (1<<4 - 1)))
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case arg_R1_12:
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return Reg(((x >> 12) & (1<<4 - 1)))
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case arg_R2_0:
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return Reg((x & (1<<4 - 1)) | 1)
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case arg_R2_12:
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return Reg(((x >> 12) & (1<<4 - 1)) | 1)
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case arg_SP:
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return SP
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case arg_Sd_Dd:
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v := (x >> 12) & (1<<4 - 1)
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vx := (x >> 22) & 1
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sz := (x >> 8) & 1
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if sz != 0 {
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return D0 + Reg(vx<<4+v)
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} else {
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return S0 + Reg(v<<1+vx)
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}
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case arg_Dd_Sd:
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return decodeArg(arg_Sd_Dd, x^(1<<8))
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case arg_Sd:
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v := (x >> 12) & (1<<4 - 1)
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vx := (x >> 22) & 1
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return S0 + Reg(v<<1+vx)
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case arg_Sm_Dm:
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v := (x >> 0) & (1<<4 - 1)
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vx := (x >> 5) & 1
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sz := (x >> 8) & 1
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if sz != 0 {
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return D0 + Reg(vx<<4+v)
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} else {
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return S0 + Reg(v<<1+vx)
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}
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case arg_Sm:
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v := (x >> 0) & (1<<4 - 1)
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vx := (x >> 5) & 1
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return S0 + Reg(v<<1+vx)
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case arg_Dn_half:
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v := (x >> 16) & (1<<4 - 1)
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vx := (x >> 7) & 1
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return RegX{D0 + Reg(vx<<4+v), int((x >> 21) & 1)}
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case arg_Sn_Dn:
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v := (x >> 16) & (1<<4 - 1)
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vx := (x >> 7) & 1
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sz := (x >> 8) & 1
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if sz != 0 {
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return D0 + Reg(vx<<4+v)
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} else {
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return S0 + Reg(v<<1+vx)
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}
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case arg_Sn:
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v := (x >> 16) & (1<<4 - 1)
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vx := (x >> 7) & 1
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return S0 + Reg(v<<1+vx)
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case arg_const:
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v := x & (1<<8 - 1)
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rot := (x >> 8) & (1<<4 - 1) * 2
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if rot > 0 && v&3 == 0 {
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// could rotate less
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return ImmAlt{uint8(v), uint8(rot)}
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}
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if rot >= 24 && ((v<<(32-rot))&0xFF)>>(32-rot) == v {
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// could wrap around to rot==0.
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return ImmAlt{uint8(v), uint8(rot)}
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}
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return Imm(v>>rot | v<<(32-rot))
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case arg_endian:
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return Endian((x >> 9) & 1)
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case arg_fbits:
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return Imm((16 << ((x >> 7) & 1)) - ((x&(1<<4-1))<<1 | (x>>5)&1))
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case arg_fp_0:
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return Imm(0)
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case arg_imm24:
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return Imm(x & (1<<24 - 1))
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case arg_imm5:
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return Imm((x >> 7) & (1<<5 - 1))
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case arg_imm5_32:
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x = (x >> 7) & (1<<5 - 1)
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if x == 0 {
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x = 32
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}
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return Imm(x)
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case arg_imm5_nz:
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x = (x >> 7) & (1<<5 - 1)
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if x == 0 {
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return nil
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}
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return Imm(x)
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case arg_imm_4at16_12at0:
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return Imm((x>>16)&(1<<4-1)<<12 | x&(1<<12-1))
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case arg_imm_12at8_4at0:
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return Imm((x>>8)&(1<<12-1)<<4 | x&(1<<4-1))
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case arg_imm_vfp:
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x = (x>>16)&(1<<4-1)<<4 | x&(1<<4-1)
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return Imm(x)
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case arg_label24:
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imm := (x & (1<<24 - 1)) << 2
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return PCRel(int32(imm<<6) >> 6)
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case arg_label24H:
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h := (x >> 24) & 1
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imm := (x&(1<<24-1))<<2 | h<<1
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return PCRel(int32(imm<<6) >> 6)
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case arg_label_m_12:
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d := int32(x & (1<<12 - 1))
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return Mem{Base: PC, Mode: AddrOffset, Offset: int16(-d)}
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case arg_label_p_12:
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d := int32(x & (1<<12 - 1))
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return Mem{Base: PC, Mode: AddrOffset, Offset: int16(d)}
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case arg_label_pm_12:
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d := int32(x & (1<<12 - 1))
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u := (x >> 23) & 1
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if u == 0 {
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d = -d
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}
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return Mem{Base: PC, Mode: AddrOffset, Offset: int16(d)}
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case arg_label_pm_4_4:
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d := int32((x>>8)&(1<<4-1)<<4 | x&(1<<4-1))
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u := (x >> 23) & 1
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if u == 0 {
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d = -d
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}
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return PCRel(d)
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case arg_lsb_width:
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lsb := (x >> 7) & (1<<5 - 1)
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msb := (x >> 16) & (1<<5 - 1)
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if msb < lsb || msb >= 32 {
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return nil
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}
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return Imm(msb + 1 - lsb)
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case arg_mem_R:
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Rn := Reg((x >> 16) & (1<<4 - 1))
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return Mem{Base: Rn, Mode: AddrOffset}
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case arg_mem_R_pm_R_postindex:
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// Treat [<Rn>],+/-<Rm> like [<Rn>,+/-<Rm>{,<shift>}]{!}
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// by forcing shift bits to <<0 and P=0, W=0 (postindex=true).
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return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^((1<<7-1)<<5|1<<24|1<<21))
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case arg_mem_R_pm_R_W:
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// Treat [<Rn>,+/-<Rm>]{!} like [<Rn>,+/-<Rm>{,<shift>}]{!}
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// by forcing shift bits to <<0.
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return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^((1<<7-1)<<5))
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case arg_mem_R_pm_R_shift_imm_offset:
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// Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!}
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// by forcing P=1, W=0 (index=false, wback=false).
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return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^(1<<21)|1<<24)
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case arg_mem_R_pm_R_shift_imm_postindex:
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// Treat [<Rn>],+/-<Rm>{,<shift>} like [<Rn>,+/-<Rm>{,<shift>}]{!}
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// by forcing P=0, W=0 (postindex=true).
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return decodeArg(arg_mem_R_pm_R_shift_imm_W, x&^(1<<24|1<<21))
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case arg_mem_R_pm_R_shift_imm_W:
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Rn := Reg((x >> 16) & (1<<4 - 1))
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Rm := Reg(x & (1<<4 - 1))
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typ, count := decodeShift(x)
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u := (x >> 23) & 1
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w := (x >> 21) & 1
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p := (x >> 24) & 1
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if p == 0 && w == 1 {
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return nil
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}
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sign := int8(+1)
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if u == 0 {
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sign = -1
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}
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mode := AddrMode(uint8(p<<1) | uint8(w^1))
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return Mem{Base: Rn, Mode: mode, Sign: sign, Index: Rm, Shift: typ, Count: count}
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case arg_mem_R_pm_imm12_offset:
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// Treat [<Rn>,#+/-<imm12>] like [<Rn>{,#+/-<imm12>}]{!}
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// by forcing P=1, W=0 (index=false, wback=false).
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return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<21)|1<<24)
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case arg_mem_R_pm_imm12_postindex:
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// Treat [<Rn>],#+/-<imm12> like [<Rn>{,#+/-<imm12>}]{!}
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// by forcing P=0, W=0 (postindex=true).
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return decodeArg(arg_mem_R_pm_imm12_W, x&^(1<<24|1<<21))
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case arg_mem_R_pm_imm12_W:
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Rn := Reg((x >> 16) & (1<<4 - 1))
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u := (x >> 23) & 1
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w := (x >> 21) & 1
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p := (x >> 24) & 1
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if p == 0 && w == 1 {
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return nil
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}
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sign := int8(+1)
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if u == 0 {
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sign = -1
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}
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imm := int16(x & (1<<12 - 1))
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mode := AddrMode(uint8(p<<1) | uint8(w^1))
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return Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm}
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case arg_mem_R_pm_imm8_postindex:
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// Treat [<Rn>],#+/-<imm8> like [<Rn>{,#+/-<imm8>}]{!}
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// by forcing P=0, W=0 (postindex=true).
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return decodeArg(arg_mem_R_pm_imm8_W, x&^(1<<24|1<<21))
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case arg_mem_R_pm_imm8_W:
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Rn := Reg((x >> 16) & (1<<4 - 1))
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u := (x >> 23) & 1
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w := (x >> 21) & 1
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p := (x >> 24) & 1
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if p == 0 && w == 1 {
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return nil
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}
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sign := int8(+1)
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if u == 0 {
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sign = -1
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}
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imm := int16((x>>8)&(1<<4-1)<<4 | x&(1<<4-1))
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mode := AddrMode(uint8(p<<1) | uint8(w^1))
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return Mem{Base: Rn, Mode: mode, Offset: int16(sign) * imm}
|
|
|
|
case arg_mem_R_pm_imm8at0_offset:
|
|
Rn := Reg((x >> 16) & (1<<4 - 1))
|
|
u := (x >> 23) & 1
|
|
sign := int8(+1)
|
|
if u == 0 {
|
|
sign = -1
|
|
}
|
|
imm := int16(x&(1<<8-1)) << 2
|
|
return Mem{Base: Rn, Mode: AddrOffset, Offset: int16(sign) * imm}
|
|
|
|
case arg_option:
|
|
return Imm(x & (1<<4 - 1))
|
|
|
|
case arg_registers:
|
|
return RegList(x & (1<<16 - 1))
|
|
|
|
case arg_registers2:
|
|
x &= 1<<16 - 1
|
|
n := 0
|
|
for i := 0; i < 16; i++ {
|
|
if x>>uint(i)&1 != 0 {
|
|
n++
|
|
}
|
|
}
|
|
if n < 2 {
|
|
return nil
|
|
}
|
|
return RegList(x)
|
|
|
|
case arg_registers1:
|
|
Rt := (x >> 12) & (1<<4 - 1)
|
|
return RegList(1 << Rt)
|
|
|
|
case arg_satimm4:
|
|
return Imm((x >> 16) & (1<<4 - 1))
|
|
|
|
case arg_satimm5:
|
|
return Imm((x >> 16) & (1<<5 - 1))
|
|
|
|
case arg_satimm4m1:
|
|
return Imm((x>>16)&(1<<4-1) + 1)
|
|
|
|
case arg_satimm5m1:
|
|
return Imm((x>>16)&(1<<5-1) + 1)
|
|
|
|
case arg_widthm1:
|
|
return Imm((x>>16)&(1<<5-1) + 1)
|
|
|
|
}
|
|
}
|
|
|
|
// decodeShift decodes the shift-by-immediate encoded in x.
|
|
func decodeShift(x uint32) (Shift, uint8) {
|
|
count := (x >> 7) & (1<<5 - 1)
|
|
typ := Shift((x >> 5) & (1<<2 - 1))
|
|
switch typ {
|
|
case ShiftRight, ShiftRightSigned:
|
|
if count == 0 {
|
|
count = 32
|
|
}
|
|
case RotateRight:
|
|
if count == 0 {
|
|
typ = RotateRightExt
|
|
count = 1
|
|
}
|
|
}
|
|
return typ, uint8(count)
|
|
}
|