mirror of
https://github.com/cwinfo/matterbridge.git
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439 lines
7.5 KiB
Go
439 lines
7.5 KiB
Go
// Copyright 2014 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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package armasm
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import (
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"bytes"
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"fmt"
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)
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// A Mode is an instruction execution mode.
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type Mode int
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const (
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_ Mode = iota
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ModeARM
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ModeThumb
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)
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func (m Mode) String() string {
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switch m {
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case ModeARM:
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return "ARM"
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case ModeThumb:
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return "Thumb"
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}
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return fmt.Sprintf("Mode(%d)", int(m))
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}
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// An Op is an ARM opcode.
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type Op uint16
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// NOTE: The actual Op values are defined in tables.go.
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// They are chosen to simplify instruction decoding and
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// are not a dense packing from 0 to N, although the
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// density is high, probably at least 90%.
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func (op Op) String() string {
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if op >= Op(len(opstr)) || opstr[op] == "" {
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return fmt.Sprintf("Op(%d)", int(op))
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}
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return opstr[op]
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}
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// An Inst is a single instruction.
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type Inst struct {
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Op Op // Opcode mnemonic
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Enc uint32 // Raw encoding bits.
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Len int // Length of encoding in bytes.
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Args Args // Instruction arguments, in ARM manual order.
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}
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func (i Inst) String() string {
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var buf bytes.Buffer
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buf.WriteString(i.Op.String())
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for j, arg := range i.Args {
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if arg == nil {
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break
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}
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if j == 0 {
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buf.WriteString(" ")
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} else {
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buf.WriteString(", ")
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}
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buf.WriteString(arg.String())
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}
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return buf.String()
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}
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// An Args holds the instruction arguments.
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// If an instruction has fewer than 4 arguments,
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// the final elements in the array are nil.
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type Args [4]Arg
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// An Arg is a single instruction argument, one of these types:
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// Endian, Imm, Mem, PCRel, Reg, RegList, RegShift, RegShiftReg.
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type Arg interface {
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IsArg()
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String() string
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}
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type Float32Imm float32
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func (Float32Imm) IsArg() {}
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func (f Float32Imm) String() string {
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return fmt.Sprintf("#%v", float32(f))
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}
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type Float64Imm float32
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func (Float64Imm) IsArg() {}
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func (f Float64Imm) String() string {
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return fmt.Sprintf("#%v", float64(f))
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}
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// An Imm is an integer constant.
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type Imm uint32
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func (Imm) IsArg() {}
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func (i Imm) String() string {
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return fmt.Sprintf("#%#x", uint32(i))
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}
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// A ImmAlt is an alternate encoding of an integer constant.
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type ImmAlt struct {
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Val uint8
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Rot uint8
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}
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func (ImmAlt) IsArg() {}
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func (i ImmAlt) Imm() Imm {
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v := uint32(i.Val)
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r := uint(i.Rot)
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return Imm(v>>r | v<<(32-r))
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}
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func (i ImmAlt) String() string {
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return fmt.Sprintf("#%#x, %d", i.Val, i.Rot)
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}
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// A Label is a text (code) address.
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type Label uint32
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func (Label) IsArg() {}
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func (i Label) String() string {
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return fmt.Sprintf("%#x", uint32(i))
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}
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// A Reg is a single register.
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// The zero value denotes R0, not the absence of a register.
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type Reg uint8
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const (
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R0 Reg = iota
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R1
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R2
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R3
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R4
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R5
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R6
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R7
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R8
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R9
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R10
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R11
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R12
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R13
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R14
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R15
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S0
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S1
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S2
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S3
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S4
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S5
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S6
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S7
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S8
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S9
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S10
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S11
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S12
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S13
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S14
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S15
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S16
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S17
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S18
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S19
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S20
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S21
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S22
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S23
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S24
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S25
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S26
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S27
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S28
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S29
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S30
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S31
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D0
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D1
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D2
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D3
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D4
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D5
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D6
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D7
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D8
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D9
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D10
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D11
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D12
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D13
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D14
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D15
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D16
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D17
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D18
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D19
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D20
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D21
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D22
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D23
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D24
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D25
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D26
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D27
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D28
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D29
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D30
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D31
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APSR
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APSR_nzcv
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FPSCR
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SP = R13
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LR = R14
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PC = R15
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)
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func (Reg) IsArg() {}
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func (r Reg) String() string {
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switch r {
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case APSR:
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return "APSR"
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case APSR_nzcv:
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return "APSR_nzcv"
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case FPSCR:
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return "FPSCR"
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case SP:
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return "SP"
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case PC:
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return "PC"
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case LR:
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return "LR"
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}
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if R0 <= r && r <= R15 {
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return fmt.Sprintf("R%d", int(r-R0))
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}
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if S0 <= r && r <= S31 {
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return fmt.Sprintf("S%d", int(r-S0))
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}
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if D0 <= r && r <= D31 {
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return fmt.Sprintf("D%d", int(r-D0))
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}
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return fmt.Sprintf("Reg(%d)", int(r))
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}
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// A RegX represents a fraction of a multi-value register.
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// The Index field specifies the index number,
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// but the size of the fraction is not specified.
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// It must be inferred from the instruction and the register type.
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// For example, in a VMOV instruction, RegX{D5, 1} represents
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// the top 32 bits of the 64-bit D5 register.
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type RegX struct {
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Reg Reg
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Index int
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}
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func (RegX) IsArg() {}
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func (r RegX) String() string {
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return fmt.Sprintf("%s[%d]", r.Reg, r.Index)
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}
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// A RegList is a register list.
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// Bits at indexes x = 0 through 15 indicate whether the corresponding Rx register is in the list.
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type RegList uint16
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func (RegList) IsArg() {}
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func (r RegList) String() string {
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var buf bytes.Buffer
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fmt.Fprintf(&buf, "{")
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sep := ""
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for i := 0; i < 16; i++ {
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if r&(1<<uint(i)) != 0 {
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fmt.Fprintf(&buf, "%s%s", sep, Reg(i).String())
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sep = ","
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}
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}
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fmt.Fprintf(&buf, "}")
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return buf.String()
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}
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// An Endian is the argument to the SETEND instruction.
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type Endian uint8
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const (
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LittleEndian Endian = 0
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BigEndian Endian = 1
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)
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func (Endian) IsArg() {}
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func (e Endian) String() string {
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if e != 0 {
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return "BE"
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}
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return "LE"
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}
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// A Shift describes an ARM shift operation.
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type Shift uint8
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const (
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ShiftLeft Shift = 0 // left shift
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ShiftRight Shift = 1 // logical (unsigned) right shift
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ShiftRightSigned Shift = 2 // arithmetic (signed) right shift
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RotateRight Shift = 3 // right rotate
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RotateRightExt Shift = 4 // right rotate through carry (Count will always be 1)
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)
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var shiftName = [...]string{
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"LSL", "LSR", "ASR", "ROR", "RRX",
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}
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func (s Shift) String() string {
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if s < 5 {
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return shiftName[s]
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}
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return fmt.Sprintf("Shift(%d)", int(s))
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}
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// A RegShift is a register shifted by a constant.
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type RegShift struct {
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Reg Reg
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Shift Shift
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Count uint8
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}
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func (RegShift) IsArg() {}
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func (r RegShift) String() string {
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return fmt.Sprintf("%s %s #%d", r.Reg, r.Shift, r.Count)
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}
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// A RegShiftReg is a register shifted by a register.
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type RegShiftReg struct {
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Reg Reg
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Shift Shift
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RegCount Reg
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}
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func (RegShiftReg) IsArg() {}
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func (r RegShiftReg) String() string {
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return fmt.Sprintf("%s %s %s", r.Reg, r.Shift, r.RegCount)
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}
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// A PCRel describes a memory address (usually a code label)
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// as a distance relative to the program counter.
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// TODO(rsc): Define which program counter (PC+4? PC+8? PC?).
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type PCRel int32
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func (PCRel) IsArg() {}
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func (r PCRel) String() string {
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return fmt.Sprintf("PC%+#x", int32(r))
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}
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// An AddrMode is an ARM addressing mode.
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type AddrMode uint8
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const (
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_ AddrMode = iota
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AddrPostIndex // [R], X – use address R, set R = R + X
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AddrPreIndex // [R, X]! – use address R + X, set R = R + X
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AddrOffset // [R, X] – use address R + X
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AddrLDM // R – [R] but formats as R, for LDM/STM only
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AddrLDM_WB // R! - [R], X where X is instruction-specific amount, for LDM/STM only
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)
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// A Mem is a memory reference made up of a base R and index expression X.
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// The effective memory address is R or R+X depending on AddrMode.
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// The index expression is X = Sign*(Index Shift Count) + Offset,
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// but in any instruction either Sign = 0 or Offset = 0.
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type Mem struct {
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Base Reg
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Mode AddrMode
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Sign int8
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Index Reg
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Shift Shift
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Count uint8
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Offset int16
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}
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func (Mem) IsArg() {}
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func (m Mem) String() string {
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R := m.Base.String()
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X := ""
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if m.Sign != 0 {
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X = "+"
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if m.Sign < 0 {
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X = "-"
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}
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X += m.Index.String()
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if m.Shift != ShiftLeft || m.Count != 0 {
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X += fmt.Sprintf(", %s #%d", m.Shift, m.Count)
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}
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} else {
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X = fmt.Sprintf("#%d", m.Offset)
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}
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switch m.Mode {
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case AddrOffset:
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if X == "#0" {
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return fmt.Sprintf("[%s]", R)
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}
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return fmt.Sprintf("[%s, %s]", R, X)
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case AddrPreIndex:
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return fmt.Sprintf("[%s, %s]!", R, X)
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case AddrPostIndex:
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return fmt.Sprintf("[%s], %s", R, X)
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case AddrLDM:
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if X == "#0" {
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return R
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}
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case AddrLDM_WB:
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if X == "#0" {
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return R + "!"
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}
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}
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return fmt.Sprintf("[%s Mode(%d) %s]", R, int(m.Mode), X)
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}
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