mirror of
https://github.com/cwinfo/matterbridge.git
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380 lines
9.3 KiB
ArmAsm
380 lines
9.3 KiB
ArmAsm
// Copyright 2015 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// This code was translated into a form compatible with 5a from the public
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// domain source by Andrew Moon: github.com/floodyberry/poly1305-opt/blob/master/app/extensions/poly1305.
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// +build arm,!gccgo,!appengine
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DATA poly1305_init_constants_armv6<>+0x00(SB)/4, $0x3ffffff
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DATA poly1305_init_constants_armv6<>+0x04(SB)/4, $0x3ffff03
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DATA poly1305_init_constants_armv6<>+0x08(SB)/4, $0x3ffc0ff
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DATA poly1305_init_constants_armv6<>+0x0c(SB)/4, $0x3f03fff
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DATA poly1305_init_constants_armv6<>+0x10(SB)/4, $0x00fffff
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GLOBL poly1305_init_constants_armv6<>(SB), 8, $20
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// Warning: the linker may use R11 to synthesize certain instructions. Please
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// take care and verify that no synthetic instructions use it.
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TEXT poly1305_init_ext_armv6<>(SB),4,$-4
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MOVM.DB.W [R4-R11], (R13)
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MOVM.IA.W (R1), [R2-R5]
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MOVW $poly1305_init_constants_armv6<>(SB), R7
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MOVW R2, R8
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MOVW R2>>26, R9
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MOVW R3>>20, g
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MOVW R4>>14, R11
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MOVW R5>>8, R12
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ORR R3<<6, R9, R9
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ORR R4<<12, g, g
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ORR R5<<18, R11, R11
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MOVM.IA (R7), [R2-R6]
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AND R8, R2, R2
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AND R9, R3, R3
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AND g, R4, R4
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AND R11, R5, R5
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AND R12, R6, R6
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MOVM.IA.W [R2-R6], (R0)
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EOR R2, R2, R2
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EOR R3, R3, R3
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EOR R4, R4, R4
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EOR R5, R5, R5
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EOR R6, R6, R6
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MOVM.IA.W [R2-R6], (R0)
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MOVM.IA.W (R1), [R2-R5]
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MOVM.IA [R2-R6], (R0)
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MOVM.IA.W (R13), [R4-R11]
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RET
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#define MOVW_UNALIGNED(Rsrc, Rdst, Rtmp, offset) \
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MOVBU (offset+0)(Rsrc), Rtmp; \
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MOVBU Rtmp, (offset+0)(Rdst); \
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MOVBU (offset+1)(Rsrc), Rtmp; \
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MOVBU Rtmp, (offset+1)(Rdst); \
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MOVBU (offset+2)(Rsrc), Rtmp; \
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MOVBU Rtmp, (offset+2)(Rdst); \
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MOVBU (offset+3)(Rsrc), Rtmp; \
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MOVBU Rtmp, (offset+3)(Rdst)
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TEXT poly1305_blocks_armv6<>(SB),4,$-4
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MOVM.DB.W [R4, R5, R6, R7, R8, R9, g, R11, R14], (R13)
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SUB $128, R13
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MOVW R0, 36(R13)
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MOVW R1, 40(R13)
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MOVW R2, 44(R13)
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MOVW R1, R14
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MOVW R2, R12
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MOVW 56(R0), R8
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WORD $0xe1180008 // TST R8, R8 not working see issue 5921
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EOR R6, R6, R6
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MOVW.EQ $(1<<24), R6
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MOVW R6, 32(R13)
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ADD $64, R13, g
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MOVM.IA (R0), [R0-R9]
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MOVM.IA [R0-R4], (g)
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CMP $16, R12
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BLO poly1305_blocks_armv6_done
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poly1305_blocks_armv6_mainloop:
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WORD $0xe31e0003 // TST R14, #3 not working see issue 5921
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BEQ poly1305_blocks_armv6_mainloop_aligned
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ADD $48, R13, g
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MOVW_UNALIGNED(R14, g, R0, 0)
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MOVW_UNALIGNED(R14, g, R0, 4)
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MOVW_UNALIGNED(R14, g, R0, 8)
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MOVW_UNALIGNED(R14, g, R0, 12)
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MOVM.IA (g), [R0-R3]
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ADD $16, R14
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B poly1305_blocks_armv6_mainloop_loaded
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poly1305_blocks_armv6_mainloop_aligned:
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MOVM.IA.W (R14), [R0-R3]
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poly1305_blocks_armv6_mainloop_loaded:
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MOVW R0>>26, g
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MOVW R1>>20, R11
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MOVW R2>>14, R12
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MOVW R14, 40(R13)
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MOVW R3>>8, R4
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ORR R1<<6, g, g
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ORR R2<<12, R11, R11
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ORR R3<<18, R12, R12
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BIC $0xfc000000, R0, R0
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BIC $0xfc000000, g, g
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MOVW 32(R13), R3
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BIC $0xfc000000, R11, R11
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BIC $0xfc000000, R12, R12
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ADD R0, R5, R5
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ADD g, R6, R6
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ORR R3, R4, R4
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ADD R11, R7, R7
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ADD $64, R13, R14
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ADD R12, R8, R8
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ADD R4, R9, R9
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MOVM.IA (R14), [R0-R4]
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MULLU R4, R5, (R11, g)
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MULLU R3, R5, (R14, R12)
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MULALU R3, R6, (R11, g)
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MULALU R2, R6, (R14, R12)
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MULALU R2, R7, (R11, g)
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MULALU R1, R7, (R14, R12)
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ADD R4<<2, R4, R4
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ADD R3<<2, R3, R3
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MULALU R1, R8, (R11, g)
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MULALU R0, R8, (R14, R12)
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MULALU R0, R9, (R11, g)
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MULALU R4, R9, (R14, R12)
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MOVW g, 24(R13)
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MOVW R11, 28(R13)
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MOVW R12, 16(R13)
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MOVW R14, 20(R13)
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MULLU R2, R5, (R11, g)
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MULLU R1, R5, (R14, R12)
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MULALU R1, R6, (R11, g)
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MULALU R0, R6, (R14, R12)
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MULALU R0, R7, (R11, g)
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MULALU R4, R7, (R14, R12)
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ADD R2<<2, R2, R2
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ADD R1<<2, R1, R1
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MULALU R4, R8, (R11, g)
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MULALU R3, R8, (R14, R12)
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MULALU R3, R9, (R11, g)
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MULALU R2, R9, (R14, R12)
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MOVW g, 8(R13)
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MOVW R11, 12(R13)
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MOVW R12, 0(R13)
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MOVW R14, w+4(SP)
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MULLU R0, R5, (R11, g)
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MULALU R4, R6, (R11, g)
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MULALU R3, R7, (R11, g)
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MULALU R2, R8, (R11, g)
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MULALU R1, R9, (R11, g)
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MOVM.IA (R13), [R0-R7]
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MOVW g>>26, R12
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MOVW R4>>26, R14
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ORR R11<<6, R12, R12
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ORR R5<<6, R14, R14
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BIC $0xfc000000, g, g
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BIC $0xfc000000, R4, R4
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ADD.S R12, R0, R0
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ADC $0, R1, R1
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ADD.S R14, R6, R6
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ADC $0, R7, R7
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MOVW R0>>26, R12
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MOVW R6>>26, R14
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ORR R1<<6, R12, R12
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ORR R7<<6, R14, R14
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BIC $0xfc000000, R0, R0
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BIC $0xfc000000, R6, R6
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ADD R14<<2, R14, R14
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ADD.S R12, R2, R2
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ADC $0, R3, R3
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ADD R14, g, g
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MOVW R2>>26, R12
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MOVW g>>26, R14
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ORR R3<<6, R12, R12
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BIC $0xfc000000, g, R5
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BIC $0xfc000000, R2, R7
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ADD R12, R4, R4
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ADD R14, R0, R0
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MOVW R4>>26, R12
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BIC $0xfc000000, R4, R8
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ADD R12, R6, R9
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MOVW w+44(SP), R12
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MOVW w+40(SP), R14
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MOVW R0, R6
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CMP $32, R12
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SUB $16, R12, R12
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MOVW R12, 44(R13)
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BHS poly1305_blocks_armv6_mainloop
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poly1305_blocks_armv6_done:
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MOVW 36(R13), R12
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MOVW R5, 20(R12)
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MOVW R6, 24(R12)
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MOVW R7, 28(R12)
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MOVW R8, 32(R12)
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MOVW R9, 36(R12)
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ADD $128, R13, R13
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MOVM.IA.W (R13), [R4, R5, R6, R7, R8, R9, g, R11, R14]
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RET
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#define MOVHUP_UNALIGNED(Rsrc, Rdst, Rtmp) \
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MOVBU.P 1(Rsrc), Rtmp; \
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MOVBU.P Rtmp, 1(Rdst); \
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MOVBU.P 1(Rsrc), Rtmp; \
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MOVBU.P Rtmp, 1(Rdst)
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#define MOVWP_UNALIGNED(Rsrc, Rdst, Rtmp) \
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MOVHUP_UNALIGNED(Rsrc, Rdst, Rtmp); \
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MOVHUP_UNALIGNED(Rsrc, Rdst, Rtmp)
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TEXT poly1305_finish_ext_armv6<>(SB),4,$-4
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MOVM.DB.W [R4, R5, R6, R7, R8, R9, g, R11, R14], (R13)
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SUB $16, R13, R13
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MOVW R0, R5
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MOVW R1, R6
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MOVW R2, R7
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MOVW R3, R8
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AND.S R2, R2, R2
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BEQ poly1305_finish_ext_armv6_noremaining
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EOR R0, R0
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MOVW R13, R9
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MOVW R0, 0(R13)
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MOVW R0, 4(R13)
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MOVW R0, 8(R13)
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MOVW R0, 12(R13)
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WORD $0xe3110003 // TST R1, #3 not working see issue 5921
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BEQ poly1305_finish_ext_armv6_aligned
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WORD $0xe3120008 // TST R2, #8 not working see issue 5921
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BEQ poly1305_finish_ext_armv6_skip8
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MOVWP_UNALIGNED(R1, R9, g)
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MOVWP_UNALIGNED(R1, R9, g)
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poly1305_finish_ext_armv6_skip8:
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WORD $0xe3120004 // TST $4, R2 not working see issue 5921
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BEQ poly1305_finish_ext_armv6_skip4
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MOVWP_UNALIGNED(R1, R9, g)
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poly1305_finish_ext_armv6_skip4:
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WORD $0xe3120002 // TST $2, R2 not working see issue 5921
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BEQ poly1305_finish_ext_armv6_skip2
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MOVHUP_UNALIGNED(R1, R9, g)
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B poly1305_finish_ext_armv6_skip2
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poly1305_finish_ext_armv6_aligned:
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WORD $0xe3120008 // TST R2, #8 not working see issue 5921
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BEQ poly1305_finish_ext_armv6_skip8_aligned
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MOVM.IA.W (R1), [g-R11]
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MOVM.IA.W [g-R11], (R9)
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poly1305_finish_ext_armv6_skip8_aligned:
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WORD $0xe3120004 // TST $4, R2 not working see issue 5921
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BEQ poly1305_finish_ext_armv6_skip4_aligned
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MOVW.P 4(R1), g
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MOVW.P g, 4(R9)
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poly1305_finish_ext_armv6_skip4_aligned:
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WORD $0xe3120002 // TST $2, R2 not working see issue 5921
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BEQ poly1305_finish_ext_armv6_skip2
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MOVHU.P 2(R1), g
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MOVH.P g, 2(R9)
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poly1305_finish_ext_armv6_skip2:
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WORD $0xe3120001 // TST $1, R2 not working see issue 5921
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BEQ poly1305_finish_ext_armv6_skip1
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MOVBU.P 1(R1), g
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MOVBU.P g, 1(R9)
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poly1305_finish_ext_armv6_skip1:
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MOVW $1, R11
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MOVBU R11, 0(R9)
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MOVW R11, 56(R5)
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MOVW R5, R0
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MOVW R13, R1
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MOVW $16, R2
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BL poly1305_blocks_armv6<>(SB)
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poly1305_finish_ext_armv6_noremaining:
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MOVW 20(R5), R0
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MOVW 24(R5), R1
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MOVW 28(R5), R2
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MOVW 32(R5), R3
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MOVW 36(R5), R4
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MOVW R4>>26, R12
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BIC $0xfc000000, R4, R4
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ADD R12<<2, R12, R12
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ADD R12, R0, R0
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MOVW R0>>26, R12
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BIC $0xfc000000, R0, R0
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ADD R12, R1, R1
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MOVW R1>>26, R12
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BIC $0xfc000000, R1, R1
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ADD R12, R2, R2
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MOVW R2>>26, R12
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BIC $0xfc000000, R2, R2
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ADD R12, R3, R3
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MOVW R3>>26, R12
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BIC $0xfc000000, R3, R3
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ADD R12, R4, R4
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ADD $5, R0, R6
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MOVW R6>>26, R12
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BIC $0xfc000000, R6, R6
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ADD R12, R1, R7
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MOVW R7>>26, R12
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BIC $0xfc000000, R7, R7
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ADD R12, R2, g
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MOVW g>>26, R12
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BIC $0xfc000000, g, g
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ADD R12, R3, R11
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MOVW $-(1<<26), R12
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ADD R11>>26, R12, R12
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BIC $0xfc000000, R11, R11
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ADD R12, R4, R14
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MOVW R14>>31, R12
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SUB $1, R12
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AND R12, R6, R6
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AND R12, R7, R7
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AND R12, g, g
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AND R12, R11, R11
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AND R12, R14, R14
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MVN R12, R12
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AND R12, R0, R0
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AND R12, R1, R1
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AND R12, R2, R2
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AND R12, R3, R3
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AND R12, R4, R4
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ORR R6, R0, R0
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ORR R7, R1, R1
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ORR g, R2, R2
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ORR R11, R3, R3
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ORR R14, R4, R4
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ORR R1<<26, R0, R0
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MOVW R1>>6, R1
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ORR R2<<20, R1, R1
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MOVW R2>>12, R2
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ORR R3<<14, R2, R2
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MOVW R3>>18, R3
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ORR R4<<8, R3, R3
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MOVW 40(R5), R6
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MOVW 44(R5), R7
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MOVW 48(R5), g
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MOVW 52(R5), R11
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ADD.S R6, R0, R0
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ADC.S R7, R1, R1
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ADC.S g, R2, R2
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ADC.S R11, R3, R3
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MOVM.IA [R0-R3], (R8)
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MOVW R5, R12
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EOR R0, R0, R0
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EOR R1, R1, R1
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EOR R2, R2, R2
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EOR R3, R3, R3
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EOR R4, R4, R4
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EOR R5, R5, R5
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EOR R6, R6, R6
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EOR R7, R7, R7
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MOVM.IA.W [R0-R7], (R12)
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MOVM.IA [R0-R7], (R12)
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ADD $16, R13, R13
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MOVM.IA.W (R13), [R4, R5, R6, R7, R8, R9, g, R11, R14]
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RET
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// func poly1305_auth_armv6(out *[16]byte, m *byte, mlen uint32, key *[32]key)
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TEXT ·poly1305_auth_armv6(SB),0,$280-16
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MOVW out+0(FP), R4
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MOVW m+4(FP), R5
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MOVW mlen+8(FP), R6
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MOVW key+12(FP), R7
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MOVW R13, R8
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BIC $63, R13
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SUB $64, R13, R13
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MOVW R13, R0
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MOVW R7, R1
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BL poly1305_init_ext_armv6<>(SB)
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BIC.S $15, R6, R2
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BEQ poly1305_auth_armv6_noblocks
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MOVW R13, R0
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MOVW R5, R1
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ADD R2, R5, R5
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SUB R2, R6, R6
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BL poly1305_blocks_armv6<>(SB)
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poly1305_auth_armv6_noblocks:
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MOVW R13, R0
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MOVW R5, R1
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MOVW R6, R2
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MOVW R4, R3
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BL poly1305_finish_ext_armv6<>(SB)
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MOVW R8, R13
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RET
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